a86_shifter.v

来自「intel 8088 架构的verilog代码」· Verilog 代码 · 共 58 行

// http://gforge.openchip.org/projects/a86

// 16 Bit Barrel Shifter

`include "timescale.v"
`include "a86_defines.v"

module a86_shifter(
  shop,cl,imm8,
  cin,cout,din,dout
  );
    
input [7:0] shop;
input [7:0] cl;
input [7:0] imm8;
input cin;
output cout;
input [15:0] din;
output [15:0] dout;

reg [15:0] dout;

reg [15:0] shift_result;

reg [15:0] rol_result;
reg [15:0] ror_result;

reg [3:0] shift_cnt;

// shift by one, CL or IMM8

always @ (shop,cl,imm8)
   if (shop[7]) shift_cnt <= 4'b0001;
   else if (shop[6]) shift_cnt <= cl[3:0];
        else shift_cnt <= imm8[3:0];

always @ (din)
   rol_result <= din >> shift_cnt; 

always @ (din)
   ror_result <= din << shift_cnt; 


always @ (shop)
  case(shop[3:0])
    `shift_op_rol: shift_result <= rol_result; 
    `shift_op_ror: shift_result <= ror_result; 
    default shift_result <= 16'h0000;
  endcase  

// todo if shift_cnt >15 then return 0, as all bits are shifted out

always @ (shift_result)
  dout <= shift_result;


endmodule