a86_ifetch.v

来自「intel 8088 架构的verilog代码」· Verilog 代码 · 共 53 行

// http://gforge.openchip.org/projects/a86

//
// Instrcution Fetch
// when empty, instruction bytes will start to fill from i1 to i5 until empty
//

`include "timescale.v"

module a86_ifetch(clk,empty,i0,i1,i2,i3,i4,i5);

input clk;
input empty;


output [7:0] i0;
output [7:0] i1;
output [7:0] i2;
output [7:0] i3;
output [7:0] i4;
output [7:0] i5;

reg [7:0] i0;
reg [7:0] i1;
reg [7:0] i2;
reg [7:0] i3;
reg [7:0] i4;
reg [7:0] i5;


// dummy

always @ (posedge clk)
  i0 <= i1;

always @ (posedge clk)
  i1 <= i2;

always @ (posedge clk)
  i2 <= i3;

always @ (posedge clk)
  i3 <= i4;

always @ (posedge clk)
  i4 <= i5;

always @ (posedge clk)
  i5 <= i5 + 1;


endmodule