a86_seg_sel.v

来自「intel 8088 架构的verilog代码」· Verilog 代码 · 共 30 行

// http://gforge.openchip.org/projects/a86

`include "timescale.v"

module a86_seg_sel(
  sel, 
  cs,ds,ss,es,
  seg
  );

input [1:0] sel;

input [15:0] cs;
input [15:0] ds;
input [15:0] ss;
input [15:0] es;

output [15:0] seg;
reg [15:0] seg; 

always @ (sel,ds,ss,es,cs)
  case(sel)
    2'b01: seg = ds; 
    2'b10: seg = ss; 
    2'b11: seg = es; 
    default seg = cs;
  endcase

endmodule