a86_sp.v

来自「intel 8088 架构的verilog代码」· Verilog 代码 · 共 29 行

// http://gforge.openchip.org/projects/a86

`include "timescale.v"
`include "a86_defines.v"

module a86_sp(rst,clk,we,din,sp,spop,en);

input rst;    
input clk;
input we;
input [15:0] din;
output [15:0] sp;
input [3:0] spop;
input en;

// latches
reg [15:0] sp; 



// Latch writes to sp reg
always @ (posedge clk)
  if (rst) sp <= 16'h0000;
  else
    if (we) sp <= din;


endmodule