a86_regs.v

来自「intel 8088 架构的verilog代码」· Verilog 代码 · 共 68 行

// http://gforge.openchip.org/projects/a86

`include "timescale.v"
`include "a86_defines.v"


module a86_regs(
  rst,clk,
  icode,
  we,we_hi,
  sel,din,din_hi,
  ax,dx,cx,bx,
  cx_zero
  );

input rst;    
input clk;
input [`a86_icode_width-1:0] icode;

input we;
input we_hi; // write high word of ALU result to dx

input [1:0] sel;
input [15:0] din;
input [15:0] din_hi;

output [15:0] ax;
output [15:0] dx;
output [15:0] cx;
output [15:0] bx;

output cx_zero; // CX=0 or LOOP
reg cx_zero; // CX=0 or LOOP

// latches
reg [15:0] ax; 
reg [15:0] bx; 
reg [15:0] cx; 
reg [15:0] dx; 

always @ (cx)
  if (cx == 16'h0000) cx_zero <= 1;
  else cx_zero <= 0;

reg [15:0] cx_dec;
always @(icode,cx,din) 
  if(icode[`a86_icode_dec_cx]) cx_dec = cx - 16'h0001;
  else cx_dec = din;
 

// Latch writes to seg regs
always @ (posedge clk)

  if (rst) begin
    ax <= 16'h1111;
    bx <= 16'h3333; 
    cx <= 16'h7777; 
    dx <= 16'hAAAA; 
  end else 
  begin
    if (icode[`a86_icode_wr_ax]) ax <= din;
    if (icode[`a86_icode_wr_bx]) bx <= din;
    if (icode[`a86_icode_wr_cx]) cx <= cx_dec;
    if (icode[`a86_icode_wr_dx]) dx <= din;
  end

endmodule