a86_sysace.v

intel 8088 架构的verilog代码

// http://gforge.openchip.org/projects/a86

`include "a86_defines.v"

module a86_sysace(

  iobus_addr,
  iobus_clk,
  iobus_rst,
  iobus_we,
  iobus_ce,
  iobus_be,
  iobus_data_out,
  iobus_data_in,
  iobus_busy,

  SYSACE_CLK,       // I  
  SYSACE_MPCE,      // O                
  SYSACE_MPWE,      // O
  SYSACE_MPOE,      // O
  SYSACE_MPIRQ,     // I
  SYSACE_MBRDY,     // I
  SYSACE_MPD,       // IO
  SYSACE_MPA        // O
  );
   

input [`a86_io_awidth-1:0] iobus_addr;
input iobus_clk;
input iobus_rst;
input iobus_we;
input iobus_ce;
input [1:0] iobus_be;

output [`a86_io_dwidth-1:0] iobus_data_out;
reg [`a86_io_dwidth-1:0] iobus_data_out;
input [`a86_io_dwidth-1:0] iobus_data_in;
output iobus_busy;
reg iobus_busy;




input         SYSACE_CLK;       // I
output        SYSACE_MPCE;      // O          
wire          SYSACE_MPCE;      // O          
output        SYSACE_MPWE;      // O
wire          SYSACE_MPWE;      // O          
output        SYSACE_MPOE;      // O
wire          SYSACE_MPOE;      // O
input         SYSACE_MPIRQ;     // I
input         SYSACE_MBRDY;     // I  burst not supported
inout  [15:0] SYSACE_MPD;       // IO [0:7]
wire   [15:0] SYSACE_MPD;       // IO [0:7]

output [6:0]  SYSACE_MPA;       // O [0:6]
wire   [6:0]  SYSACE_MPA;       // O [0:6]



reg sysace_base_hit;


reg [2:0] c1;



always @(iobus_addr, iobus_ce)
  sysace_base_hit = (iobus_addr[15:8] == 8'b1110_0000) & iobus_ce;


// Wait State Generator
always @ (posedge iobus_clk)
  if (iobus_rst | (sysace_base_hit == 1'b0) )
    c1 <= 3'b000;
  else c1 <= c1 + 3'b001;

// if not selected then ready, if selected then check delay counter!
always @(c1, sysace_base_hit)
  if (sysace_base_hit)
    iobus_busy = ~c1[2];
  else iobus_busy = 1'b0;

assign 
  SYSACE_MPA = iobus_addr[6:0];


assign 
  SYSACE_MPWE = ~(iobus_we & c1[1]);    // disable write
assign 
  SYSACE_MPOE = iobus_we;               // Output enable if not write
assign 
  SYSACE_MPCE = ~sysace_base_hit;       // chip select when base hit


// Read buttons!
always @ (SYSACE_MPD,sysace_base_hit) 
  if (sysace_base_hit) iobus_data_out = SYSACE_MPD;
  else iobus_data_out = 16'h0000;
                                                      

assign SYSACE_MPD = SYSACE_MPWE ? iobus_data_in : 8'bzzzzzzzzzzzzzzzz;
   
   
endmodule