a86_io_extbus.v

intel 8088 架构的verilog代码

// http://gforge.openchip.org/projects/a86

`include "timescale.v"
`include "a86_defines.v"

module a86_io_extbus(
rst,clk,icode,

core_data,
core_addr,
core_data_out,
busy2core,

iobus_addr,
iobus_clk,
iobus_rst,
iobus_we,
iobus_ce,
iobus_be,
iobus_data_out,
iobus_data_in,
iobus_busy
);
    

input rst;
input clk;


input [`a86_icode_width-1:0] icode;
input [15:0] core_data;
input [15:0] core_addr;
output [15:0] core_data_out;
output busy2core;

//
output iobus_clk;
output iobus_rst;
output iobus_we;
output iobus_ce;
wire iobus_ce;

output [`a86_io_awidth-1:0] iobus_addr;
output [1:0] iobus_be;
output [`a86_io_dwidth-1:0] iobus_data_out;



// wired-OR read bus
input [`a86_io_dwidth*`a86_io_num_devices-1:0] iobus_data_in;
// wired-OR BUSY
input [`a86_io_num_devices-1:0] iobus_busy;

// pass through
assign iobus_clk = clk;
assign iobus_rst = rst;

// I1 bit 1 is IN or OUT select :)
assign iobus_we = icode[`a86_icode_i_start+1] & icode[`a86_icode_inout];
assign iobus_be[0] = 1;
assign iobus_be[1] = icode[`a86_icode_i_start];

assign iobus_ce = icode[`a86_icode_inout];


// 
assign iobus_data_out = core_data;
assign core_data_out = 
  iobus_data_in[15:0]
  | iobus_data_in[31:16]
  | iobus_data_in[47:32]; 

assign busy2core = 
  iobus_busy[0]
  | iobus_busy[1]
  | iobus_busy[2];

// check addr size
assign iobus_addr = icode[`a86_icode_i_start+3] ? core_addr : {8'b00000000, icode[`a86_icode_i_start+15:`a86_icode_i_start+8]};



endmodule