a86_ea_calc.v

intel 8088 架构的verilog代码

// http://gforge.openchip.org/projects/a86


//
// EA (Effective Address) Calculation Module
// Calculates effective adddress based on r/m, mod and register values
//
`include "timescale.v"
`include "a86_defines.v"

/*
000 EA = (BX)+(SI)+DISP
001 EA = (BX)+(DI)+DISP
010 EA = (BP)+(SI)+DISP
011 EA = (BP)+(DI)+DISP
100 EA =      (SI)+DISP
101 EA =      (DI)+DISP
110 EA = (BP)+     DISP (except if mod=00, then EA = disp-high:disp:low)
111 EA = (BX)+     DISP
*/

module a86_ea_calc(
  ea,
  bx, bp,
  di,  si,
  disp,
  rm, mode
  );

output [15:0] ea;
input [15:0] bx;
input [15:0] bp;
input [15:0] di;
input [15:0] si;
input [15:0] disp;
input [2:0] rm;
input [1:0] mode;

reg [15:0] ea;

reg [15:0] disp_i;

always @ (mode)
  case(mode)
    2'b00: disp_i <= disp; 
    2'b01: disp_i <= disp; 
    default disp_i <= 16'h0000;
  endcase


// si di mux    
reg [15:0] si_or_di; 
always @ (rm)
  case(rm)
    `rm_bx_si_disp: si_or_di <= si; 
    `rm_bx_di_disp: si_or_di <= di;
    `rm_bp_si_disp: si_or_di <= si; 
    `rm_bp_di_disp: si_or_di <= di;
    `rm_si_disp: si_or_di <= si;
    `rm_di_disp: si_or_di <= di;
    default si_or_di <= 16'h0000;
  endcase

// bx bp mux    
reg [15:0] bx_or_bp; 
always @ (rm)
  case(rm)
    `rm_bx_si_disp: bx_or_bp <= bx;
    `rm_bx_di_disp: bx_or_bp <= bx;
    `rm_bx_disp: bx_or_bp <= bx;
    `rm_si_disp: bx_or_bp <= 16'h0000;
    `rm_di_disp: bx_or_bp <= 16'h0000;
    `rm_bp_disp: if (mode == 2'b00) bx_or_bp <= 16'h0000;
                 else bx_or_bp <= bp;
    default bx_or_bp <= bp;
  endcase

// sum it up
always @ (bx_or_bp,si_or_di,disp_i)
  ea = bx_or_bp + si_or_di + disp_i;

endmodule