a86_reg_sel.v

来自「intel 8088 架构的verilog代码」· Verilog 代码 · 共 70 行

// http://gforge.openchip.org/projects/a86

`include "timescale.v"
`include "a86_defines.v"

module a86_reg_sel(
  icode,
  rm,w,
  ax,cx,dx,bx,
  sp,bp,si,di,
  dout
  );

input [`a86_icode_width-1:0] icode;
input [2:0] rm;
input w;
input [15:0] ax;
input [15:0] cx;
input [15:0] dx;
input [15:0] bx;
input [15:0] sp;
input [15:0] bp;
input [15:0] si;
input [15:0] di;
output [15:0] dout;

reg [15:0] dout;

reg [15:0] ax_anded;
reg [15:0] bx_anded;
reg [15:0] cx_anded;
reg [15:0] dx_anded;

always @ (ax,icode)
  if (icode[`a86_icode_sel_ax]) ax_anded = ax;
  else ax_anded = 16'h0000;

always @ (bx,icode)
  if (icode[`a86_icode_sel_bx]) bx_anded = bx;
  else bx_anded = 16'h0000;

always @ (cx,icode)
  if (icode[`a86_icode_sel_cx]) cx_anded = cx;
  else cx_anded = 16'h0000;

always @ (dx,icode)
  if (icode[`a86_icode_sel_dx]) dx_anded = dx;
  else dx_anded = 16'h0000;

always @ (ax_anded,bx_anded,cx_anded,dx_anded)
  dout = ax_anded | bx_anded | cx_anded | dx_anded;

/*
always @ (rm)
  case(rm)
    3'b000: dout = ax;
    3'b001: dout = cx;
    3'b010: dout = dx;
    3'b011: dout = bx;
    3'b100: dout = sp;
    3'b101: dout = bp;
    3'b110: dout = si;
    default dout = di;
  endcase
*/  



endmodule