a86_pag.v

来自「intel 8088 架构的verilog代码」· Verilog 代码 · 共 24 行

// http://gforge.openchip.org/projects/a86
//
//
//
`include "timescale.v"

module a86_pag( 
  seg_base, offset, pa
  );
    
input [15:0] seg_base;
input [15:0] offset;

output [19:0] pa;
wire [19:0] pa;

// Calculate 20 bit Physical Address
// from Segment and Offset

assign pa = {20{seg_base,4'b0000}} + {20{4'b0000,offset}};


endmodule