📄 cnt4.vhd
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library IEEE;
use IEEE.std_logic_1164.all;
entity CNT4 is
PORT ( CLK: IN STD_LOGIC;
Q : BUFFER INTEGER RANGE 0 TO 15);
END;
ARCHITECTURE one OF CNT4 IS
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK ='1' THEN Q <= Q+1;
END IF;
END PROCESS;
END;
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