svga.tan.rpt

在开发板上实现svga条形信号发生器的源代码

; N/A   ; None         ; 16.853 ns  ; hcnt[2]    ; pixel[2] ; clock      ;
; N/A   ; None         ; 16.565 ns  ; hcnt[3]    ; pixel[0] ; clock      ;
; N/A   ; None         ; 16.374 ns  ; hcnt[2]    ; pixel[0] ; clock      ;
; N/A   ; None         ; 15.965 ns  ; hcnt[7]    ; pixel[0] ; clock      ;
; N/A   ; None         ; 15.937 ns  ; hcnt[8]    ; pixel[0] ; clock      ;
; N/A   ; None         ; 15.515 ns  ; vsync~reg0 ; vsync    ; clock      ;
; N/A   ; None         ; 14.461 ns  ; enable     ; pixel[1] ; clock      ;
; N/A   ; None         ; 14.185 ns  ; enable     ; pixel[2] ; clock      ;
; N/A   ; None         ; 13.433 ns  ; hcnt[9]    ; pixel[0] ; clock      ;
; N/A   ; None         ; 13.048 ns  ; hcnt[10]   ; pixel[0] ; clock      ;
; N/A   ; None         ; 12.046 ns  ; enable     ; pixel[0] ; clock      ;
; N/A   ; None         ; 9.160 ns   ; enable     ; blank    ; clock      ;
; N/A   ; None         ; 8.178 ns   ; hsyncint   ; hsync    ; clock      ;
+-------+--------------+------------+------------+----------+------------+


+-----------------------------------------------------------------+
; tpd                                                             ;
+-------+-------------------+-----------------+--------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From   ; To       ;
+-------+-------------------+-----------------+--------+----------+
; N/A   ; None              ; 19.797 ns       ; orient ; pixel[1] ;
; N/A   ; None              ; 19.521 ns       ; orient ; pixel[2] ;
; N/A   ; None              ; 16.893 ns       ; orient ; pixel[0] ;
+-------+-------------------+-----------------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Jan 24 10:38:07 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off SVGA -c SVGA --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "hsyncint" as buffer
Info: Clock "clock" has Internal fmax of 58.21 MHz between source register "vcnt[5]" and destination register "enable" (period= 17.18 ns)
    Info: + Longest register to register delay is 2.640 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y16_N0; Fanout = 12; REG Node = 'vcnt[5]'
        Info: 2: + IC(1.291 ns) + CELL(0.114 ns) = 1.405 ns; Loc. = LC_X29_Y17_N4; Fanout = 1; COMB Node = 'always4~64'
        Info: 3: + IC(0.452 ns) + CELL(0.292 ns) = 2.149 ns; Loc. = LC_X29_Y17_N2; Fanout = 1; COMB Node = 'always4~65'
        Info: 4: + IC(0.182 ns) + CELL(0.309 ns) = 2.640 ns; Loc. = LC_X29_Y17_N3; Fanout = 4; REG Node = 'enable'
        Info: Total cell delay = 0.715 ns ( 27.08 % )
        Info: Total interconnect delay = 1.925 ns ( 72.92 % )
    Info: - Smallest clock skew is -5.689 ns
        Info: + Shortest clock path from clock "clock" to destination register is 2.962 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 13; CLK Node = 'clock'
            Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X29_Y17_N3; Fanout = 4; REG Node = 'enable'
            Info: Total cell delay = 2.180 ns ( 73.60 % )
            Info: Total interconnect delay = 0.782 ns ( 26.40 % )
        Info: - Longest clock path from clock "clock" to source register is 8.651 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 13; CLK Node = 'clock'
            Info: 2: + IC(0.774 ns) + CELL(0.935 ns) = 3.178 ns; Loc. = LC_X16_Y13_N8; Fanout = 13; REG Node = 'hsyncint'
            Info: 3: + IC(4.762 ns) + CELL(0.711 ns) = 8.651 ns; Loc. = LC_X29_Y16_N0; Fanout = 12; REG Node = 'vcnt[5]'
            Info: Total cell delay = 3.115 ns ( 36.01 % )
            Info: Total interconnect delay = 5.536 ns ( 63.99 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tco from clock "clock" to destination pin "pixel[0]" through register "vcnt[5]" is 22.336 ns
    Info: + Longest clock path from clock "clock" to source register is 8.651 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 13; CLK Node = 'clock'
        Info: 2: + IC(0.774 ns) + CELL(0.935 ns) = 3.178 ns; Loc. = LC_X16_Y13_N8; Fanout = 13; REG Node = 'hsyncint'
        Info: 3: + IC(4.762 ns) + CELL(0.711 ns) = 8.651 ns; Loc. = LC_X29_Y16_N0; Fanout = 12; REG Node = 'vcnt[5]'
        Info: Total cell delay = 3.115 ns ( 36.01 % )
        Info: Total interconnect delay = 5.536 ns ( 63.99 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 13.461 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y16_N0; Fanout = 12; REG Node = 'vcnt[5]'
        Info: 2: + IC(1.600 ns) + CELL(0.442 ns) = 2.042 ns; Loc. = LC_X28_Y17_N1; Fanout = 1; COMB Node = 'LessThan11~216'
        Info: 3: + IC(1.243 ns) + CELL(0.114 ns) = 3.399 ns; Loc. = LC_X28_Y15_N2; Fanout = 2; COMB Node = 'LessThan11~215'
        Info: 4: + IC(1.171 ns) + CELL(0.442 ns) = 5.012 ns; Loc. = LC_X29_Y16_N8; Fanout = 1; COMB Node = 'pixel~2667'
        Info: 5: + IC(1.122 ns) + CELL(0.442 ns) = 6.576 ns; Loc. = LC_X27_Y16_N3; Fanout = 1; COMB Node = 'pixel~2668'
        Info: 6: + IC(0.407 ns) + CELL(0.442 ns) = 7.425 ns; Loc. = LC_X27_Y16_N2; Fanout = 1; COMB Node = 'pixel~2670'
        Info: 7: + IC(3.912 ns) + CELL(2.124 ns) = 13.461 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'pixel[0]'
        Info: Total cell delay = 4.006 ns ( 29.76 % )
        Info: Total interconnect delay = 9.455 ns ( 70.24 % )
Info: Longest tpd from source pin "orient" to destination pin "pixel[1]" is 19.797 ns
    Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_66; Fanout = 4; PIN Node = 'orient'
    Info: 2: + IC(8.529 ns) + CELL(0.590 ns) = 10.594 ns; Loc. = LC_X27_Y16_N4; Fanout = 2; COMB Node = 'pixel~2671'
    Info: 3: + IC(1.242 ns) + CELL(0.590 ns) = 12.426 ns; Loc. = LC_X28_Y15_N6; Fanout = 1; COMB Node = 'pixel~2674'
    Info: 4: + IC(1.237 ns)