lin.tan.rpt

来自「cpld-epm7128stc100-10驱动四位LED结果显示1234」· RPT 代码 · 共 285 行 · 第 1/3 页

; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[6]  ; lpm_counter:count_rtl_0|dffs[6]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[0]  ; lpm_counter:count_rtl_0|dffs[5]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[1]  ; lpm_counter:count_rtl_0|dffs[5]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[2]  ; lpm_counter:count_rtl_0|dffs[5]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[3]  ; lpm_counter:count_rtl_0|dffs[5]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[4]  ; lpm_counter:count_rtl_0|dffs[5]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[5]  ; lpm_counter:count_rtl_0|dffs[5]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[0]  ; lpm_counter:count_rtl_0|dffs[4]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[1]  ; lpm_counter:count_rtl_0|dffs[4]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[2]  ; lpm_counter:count_rtl_0|dffs[4]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[3]  ; lpm_counter:count_rtl_0|dffs[4]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[4]  ; lpm_counter:count_rtl_0|dffs[4]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[0]  ; lpm_counter:count_rtl_0|dffs[3]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[1]  ; lpm_counter:count_rtl_0|dffs[3]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[2]  ; lpm_counter:count_rtl_0|dffs[3]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[3]  ; lpm_counter:count_rtl_0|dffs[3]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[0]  ; lpm_counter:count_rtl_0|dffs[2]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[1]  ; lpm_counter:count_rtl_0|dffs[2]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[2]  ; lpm_counter:count_rtl_0|dffs[2]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[0]  ; lpm_counter:count_rtl_0|dffs[1]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[1]  ; lpm_counter:count_rtl_0|dffs[1]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[0]  ; lpm_counter:count_rtl_0|dffs[0]  ; clock      ; clock    ; None                        ; None                      ; None                    ;
+-------+-----------------------------------+----------------------------------+----------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------------------+
; tco                                                                                        ;
+-------+--------------+------------+----------------------------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From                             ; To     ; From Clock ;
+-------+--------------+------------+----------------------------------+--------+------------+
; N/A   ; None         ; 13.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; seg[1] ; clock      ;
; N/A   ; None         ; 13.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; seg[1] ; clock      ;
; N/A   ; None         ; 13.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; seg[2] ; clock      ;
; N/A   ; None         ; 13.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; seg[2] ; clock      ;
; N/A   ; None         ; 13.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; seg[5] ; clock      ;
; N/A   ; None         ; 13.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; seg[5] ; clock      ;
; N/A   ; None         ; 13.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; sl[0]  ; clock      ;
; N/A   ; None         ; 13.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; sl[0]  ; clock      ;
; N/A   ; None         ; 13.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; sl[1]  ; clock      ;
; N/A   ; None         ; 13.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; sl[1]  ; clock      ;
; N/A   ; None         ; 13.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; sl[2]  ; clock      ;
; N/A   ; None         ; 13.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; sl[2]  ; clock      ;
; N/A   ; None         ; 13.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; sl[3]  ; clock      ;
; N/A   ; None         ; 13.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; sl[3]  ; clock      ;
; N/A   ; None         ; 5.000 ns   ; lpm_counter:count_rtl_0|dffs[13] ; seg[4] ; clock      ;
+-------+--------------+------------+----------------------------------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Jan 03 11:53:29 2006
Info: Command: quartus_tan --import_settings_files=on --export_settings_files=off lin -c lin
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clock is an undefined clock
Info: Clock clock has Internal fmax of 100.0 MHz between source register lpm_counter:count_rtl_0|dffs[0] and destination register lpm_counter:count_rtl_0|dffs[14] (period= 10.0 ns)
    Info: + Longest register to register delay is 6.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 15; REG Node = 'lpm_counter:count_rtl_0|dffs[0]'
        Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC1; Fanout = 8; REG Node = 'lpm_counter:count_rtl_0|dffs[14]'
        Info: Total cell delay = 5.000 ns ( 83.33 % )
        Info: Total interconnect delay = 1.000 ns ( 16.67 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock clock to destination register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'clock'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC1; Fanout = 8; REG Node = 'lpm_counter:count_rtl_0|dffs[14]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
        Info: - Longest clock path from clock clock to source register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'clock'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC17; Fanout = 15; REG Node = 'lpm_counter:count_rtl_0|dffs[0]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Micro setup delay of destination is 2.000 ns
Info: tco from clock clock to destination pin seg[1] through register lpm_counter:count_rtl_0|dffs[13] is 13.000 ns
    Info: + Longest clock path from clock clock to source register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'clock'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC8; Fanout = 10; REG Node = 'lpm_counter:count_rtl_0|dffs[13]'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Longest register to pin delay is 9.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 10; REG Node = 'lpm_counter:count_rtl_0|dffs[13]'
        Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC16; Fanout = 1; COMB Node = 'seg_reg[1]~3'
        Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 9.500 ns; Loc. = PIN_92; Fanout = 0; PIN Node = 'seg[1]'
        Info: Total cell delay = 8.500 ns ( 89.47 % )
        Info: Total interconnect delay = 1.000 ns ( 10.53 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Jan 03 11:53:30 2006
    Info: Elapsed time: 00:00:00