dec21140.h
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 728 行 · 第 1/2 页
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/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 1998 Microsoft Corporation
Module Name:
Abstract:
Define DIGITAL 21140 Hardware.
Functions:
Notes:
--*/
#ifndef _DEC21140HARDWARE_
#define _DEC21140HARDWARE_
/////////////////////////////////////////////////////////////////////////////////
// Misc...
//
#define PAD(label,amt) UCHAR Pad##label[amt]
/////////////////////////////////////////////////////////////////////////////////
//
// Others...
//
typedef struct
{
DWORD dwReg;
} CSR_21140;
/////////////////////////////////////////////////////////////////////////////////
// CSR0 === Bus Mode Register
//
#define CSR0_MUST_AND 0xFFFeFFFF
#define SOFTWARE_RESET 0x00000001
#define LITTLE_ENDIAN 1 << 7
typedef struct tagCSR0
{
union
{
struct
{
DWORD SoftwareReset : 1; // [0 ] 1 = Reset all internal h/w except configuration register.
DWORD BusArbitration : 1; // [1 ] 1 = Round Robin Arbitration btw tx/rx ; 0 = Rx higher priority.
DWORD DescriptorSkipLength :5; // [2 ] Number of longwords to skip between 2 descriptors.
DWORD BigLittleEndian : 1; // [7 ] 1 = Big Endian.
DWORD ProgrammableBurstLength : 6; // [8 ] # LongWord transferred in one DMA transaction. Default 0 --> 16 DW
DWORD CacheAlignment : 2; // [14] MUST BE INITIALIZE AFTER RESET, Programmable address boundaries for
// data burst stop.
DWORD MustBeZero : 1; // [16] Must be 0.
DWORD TransmitAutomaticPolling : 3; // [17] Set to get 21140A to poll when tx buffer is unavailable.
DWORD DescriptorByteOrderingMode : 1; // [20] 1 = Big Endian ordering mode for Descriptors only.
DWORD ReadMultiple : 1; // [21] 1 = Read Multiple command on PCI bus.
DWORD Rsvd1 : 1;
DWORD ReadLnEnable : 1;
DWORD WriteInvEnable : 1;
DWORD Rsvd2 : 1;
DWORD OnNow : 1;
DWORD ________Reserved : 5;
};
DWORD dwReg;
};
} CSR0_21140;
/////////////////////////////////////////////////////////////////////////////////
// CSR5 === STATUS REGISTER
//
typedef struct tagCSR5
{
union
{
struct
{
DWORD TransmitInterrupt : 1; // [0 ] Indicates a frame transmission was completed.
DWORD TransmitProcessStopped : 1; // [1 ] Asserts when transmit process enters the stopped state.
DWORD TransmitBufferUnavailable : 1; // [2 ] Indicates next descriptor on tx list is owned by host.
DWORD TransmitJabberTimeout : 1; // [3 ] Causes TDES0[14] flag to assert.
DWORD ________Reserved_ : 1;
DWORD TransmitUnderflow : 1; // [5 ] Causes Underflow error TDES0[1] flag to be set.
DWORD ReceiveInterrupt : 1; // [6 ]
DWORD ReceiveBufferUnavailable : 1; // [7 ]
DWORD ReceiveProcessStopped : 1; // [8 ]
DWORD ReceiveWatchdogTimeout : 1; // [9 ]
DWORD EarlyTransmitInterrupt : 1; // [10] CSR5[0] automatically clears this bit.
DWORD GeneralPurposeTimerExpired : 1; // [11] CSR11 has expired.
DWORD ________Reserved__ : 1;
DWORD FatalBusError : 1; // [13] System error, 21140 will then disable all bus accesses.
DWORD ________Reserved___ : 1;
DWORD AbnormalInterruptSummary: 1; // [15] Logical OR of CSR5[1, 3, 5, 7, 8, 9, 10, 13]
DWORD NormalInterruptSummary: 1; // [16] Logical OR of CSR5[0, 2, 4, 6, 11]
DWORD ReceiveProcessState : 3; // [17] The state of receive process.
// 000 = stopped
// 001 = running [fetching descriptor]
// 010 = running [checking of end of rx packet]
// 011 = running [waitinf for rx packet]
// 100 = suspended [rx buffer unavail]
// 101 = running [closing rx descriptor]
// 110 = running [flushing current frame from rx FIFO]
// 111 = running [queuing rx frame from FIFO --> rx buffer]
DWORD TransmissionProcessState : 3; // [20] The state of tx process.
// 000 = stopped
// 001 = running [fetching tx descriptor]
// 010 = running [waiting for end of tx]
// 011 = running [Mem --> FIFO]
// 100 = reserved
// 101 = running [setup packet]
// 110 = suspended [tx FIFO underflow or tx descriptor unavail]
// 111 = running [closing tx descriptor]
DWORD ErrorBits : 3; // [23] Type of error that caused system error.
// 000 = Parity Error ... [!!! NEED TO PERFORM S/W RESET !!!]
// 001 = Master Abort
// 010 = Target Abort
DWORD ________Reserved____ : 6;
};
DWORD dwReg;
};
} CSR5_21140;
/////////////////////////////////////////////////////////////////////////////////
// CSR6 === Operating Mode Register
//
#define CSR6_MUST_AND 0xe3eeFeFF
#define CSR6_MUST_OR 0x02000000
typedef struct
{
union
{
struct
{
DWORD HashOrPerfectFilteringMode : 1; // [0 ] Read only...
DWORD StartReceive : 1; // [1 ] 1 = rx Process Running ; 0 = Rx process enters stop state.
DWORD HashOnlyFiltering : 1; // [2 ] Read only...
DWORD PassBadFrames : 1; // [3 ] 1 = Pass bad frames mode
DWORD InverseFiltering : 1; // [4 ] Read only...
DWORD StartOrStopBackoffCounter : 1; // [5 ] [suspect read only] 1 indicates internal backoff counter stops
// counting when any carrier activity is detected.
DWORD PromiscuousMode : 1; // [6 ] 1 = prosmiscuous [default state].
DWORD PassAllMulticast : 1; // [7 ] 1 = Receive all multicast packets.
DWORD ________Reserved_ : 1; // [8 ] !!! MUST BE ZERO !!!
DWORD FullDuplexMode : 1; // [9 ] 1 = full duplex mode.
DWORD OperatingMode : 2; // [10] 00 = Normal ; 01 = Internal Loop Back ; 10 = External Loop Back
DWORD ForceCollisionMode : 1; // [12] Useful only in Internal Loopback Mode.
DWORD StartTransmit : 1; // [13] 1 = Tx process running
DWORD ThresholdControlBits : 2; // [14]
DWORD ________Reserved__ : 1; // [16] !!! MUST BE ZERO !!!
DWORD CaptureEffectEnable : 1; // [17] 1 = enable resolution of the capture effect on network.
// Work together with CSR6[31]
DWORD PortSelect : 1; // [18] 1 = MII/SYM port selected ; 0 = SRL port selected.
DWORD HeartBeatDisable : 1; // [19] 1 = SQE disabled <<< MUST BE SET IN MII/SYM mode.
DWORD ________Reserved___ : 1; // [20] !!! MUST BE ZERO !!!
DWORD StoreAndForward : 1; // [21] 1 = Tx starts when full packet risides in FIFO
DWORD TransmitThresholdMode : 1; // [22] 1 = 10Mbps ; 0 = 100Mbps
DWORD PCSfunction : 1; // [23] 1 = PCS function active, MII/SYM port operates in symbol mode.
DWORD ScrambleMode : 1; // [24] 0 = MII/SYM port is not selected and CSR6[18] is also reset
// 1 = scramble function active.
DWORD ________Reserved____ : 1; // [25] !!! MUST BE ONE !!!
DWORD ________Reserved_____ : 3; // [26] !!! MUST BE ZERO !!!
DWORD ________Reserved______ : 1; // [29] Reserved.
DWORD ReceiveAll : 1; // [30] 1 = receive all regardless of destination address.
DWORD SpecialCaptureEffectEnable : 1; // [31] 1 = enables enhanced resolution, work together with CSR6[17]
};
DWORD dwReg;
};
} CSR6_21140;
/////////////////////////////////////////////////////////////////////////////////
// CSR7 === Interrupt
//
typedef struct tagCSR7
{
union
{
struct
{
DWORD TxInterruptEnable : 1; // [0 ] 1 = enable, work together with CSR7[16] and CSR5[0]
DWORD TxStoppedEnable : 1; // [1 ] 1 = enable, work together with CSR7[15] and CSR5[1]
DWORD TxBufferUnavailableEnable : 1; // [2 ] 1 = enable, work together with CSR7[16] and CSR5[2]
DWORD TxJabberTimeOutEnable : 1; // [3 ] 1 = enable, work together with CSR7[15] and CSR5[3]
DWORD ________Reserved_ : 1;
DWORD UnderFlowInterruptEnable : 1; // [5 ] 1 = enable, work together with CSR7[15] and CSR5[5]
DWORD ReceiveInterruptEnable : 1; // [6 ] 1 = enable, work together with CSR7[16] and CSR5[6]
DWORD RxBufferUnavailableEnable : 1; // [7 ] 1 = enable, work together with CSR7[15] and CSR5[7]
DWORD RxStoppedEnable : 1; // [8 ] 1 = enable, work together with CSR7[15] and CSR5[8]
DWORD RxWatchdogTimeoutEnable : 1; // [9 ] 1 = enable, work together with CSR7[15] and CSR5[9]
DWORD EarlyTxInterruptEnable : 1; // [10] 1 = enable, work together with CSR7[16] and CSR5[10]
DWORD GeneralPurposeTimerEnable : 1; // [11] 1 = enable, work together with CSR7[15] and CSR5[11]
DWORD ________Reserved__ : 1;
DWORD FatalBusErrorEnable : 1; // [13] 1 = enable, work together with CSR7[15] and CSR5[13]
DWORD ________Reserved___ : 1;
DWORD AbnormalIntrSummaryEnable : 1; // [15] 1 = enable
DWORD NormalIntrSummaryEnable : 1; // [16] 1 = enable
};
DWORD dwReg;
};
} CSR7_21140;
/////////////////////////////////////////////////////////////////////////////////
// CSR8 === Missed frames and overflow counter
//
typedef struct tagCSR8
{
union
{
struct
{
DWORD MissedFrameCounter : 16; // [0 ] Read only... # frames discarded due to host descriptor not avail
DWORD MissedFrameOverFlow : 1; // [16] Read only... Sets when missed frame counter overflows.
// Reset when CSR8 is read.
DWORD OverflowCounter : 11; // [17] Read only... # Frames discarded, due to overflow.
// Counter cleared when read.
DWORD Overflow : 1; // [28] Read only... Set when overflow counter overflows.
// Reset when CSR8 is read.
DWORD ________Reserved_ : 3;
};
DWORD dwReg;
};
} CSR8_21140;
/////////////////////////////////////////////////////////////////////////////////
// CSR9 === Boot ROM, Serial ROM, and MII Management Register
//
typedef struct tagCSR9
{
union
{
struct
{
DWORD BootRomDataOrSerialRomCtrl : 8; // [0 ] Data to be read / written to BootROM, if CSR9[12] is set.
DWORD ________Reserved_ : 2;
DWORD ExternalRegisterSelect : 1; // [10] When set 21140 selects an external register.
DWORD SerialRomSelect : 1; // [11] Select serial rom, work together with CSR9[14] or CSR9[13]
DWORD BootRomSelect : 1; // [12] 1 = select boot ROM
DWORD WriteOperation : 1; // [13] 1 = together with CSR9[12], write to boot ROM, serial ROM
// and external register.
DWORD ReadOperation : 1; // [14] 1 = together with CSR9[12], read from boot ROM, serial ROM,
// and external register.
DWORD ________Reserved__ : 1;
DWORD MiiManagementClock: 1; // [16] 1 = mii_mdc is output signal to PHY as timing reference.
DWORD MiiManagementWriteData : 1; // [17] specifies value of data 21140 writes to PHY.
DWORD MiiManagementOperationMode : 1; // [18] read or write of PHY.
DWORD MiiManagementDataIn : 1; // [19] to Read data from PHY
DWORD ________Reserved___ : 12;
};
DWORD dwReg;
};
} CSR9_21140;
/////////////////////////////////////////////////////////////////////////////////
// CSR10 === Boot ROM programming address description.
//
typedef struct tagCSR10
{
union
{
struct
{
DWORD BootRomAddress : 18 ; // [0 ] pointer to boot rom.
DWORD ________Reserved_ : 14;
};
DWORD dwReg;
};
} CSR10_21140;
/////////////////////////////////////////////////////////////////////////////////
// CSR11 === General Purpose Timer Register
//
typedef struct tagCSR11
{
union
{
struct
{
DWORD TimerValue : 16; // [0 ] Timer value.
DWORD ContinuousMode: 1; // [16] 1 = Countinuous ; 0 = one shot.
};
DWORD dwReg;
};
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