dec21140.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 728 行 · 第 1/2 页

} CSR11_21140;


/////////////////////////////////////////////////////////////////////////////////
//	CSR12 === General Purpose Port Register
//

typedef	struct tagCSR12
{
	union
	{
		struct
		{
			DWORD	GPIO : 8;						//	[0 ] 8 bit GPIO
			DWORD	GeneralPurposeControl : 1;		//	[8 ] Mode of GPIO access.
													//		1 == Mode of GPIO (input or output).
													//		0 == Output GPIO data to GPIO pin.
			DWORD	________Reserved_ : 23;		
		};

		DWORD	dwReg;
	};

} CSR12_21140;


/////////////////////////////////////////////////////////////////////////////////
//	CSR15 === Watchdog Timer Register
//

#define		CSR15_MUST_AND	0xFFFFFeFF


typedef	struct tagCSR15
{
	union
	{
		struct
		{
			DWORD	JabberDisable : 1;				//	[0 ] 1 = Transmit jabber function disable.
			DWORD	HostUnjab : 1;					//	[1 ] 1 = Transmit jabber is released immediately after jabber expiration.
													//	     0 = Transmit jabber is released 365 ms to 420 ms after jabber exp.
			DWORD	JabberClock : 1;				//	[2 ] 1 = Tx is cut off after 2048 bytes to 2560 bytes is transmitted.
													//		 0 = tx for 10Mbps port is cut off after 26 ms to 33 ms.

			DWORD	________Reserve_ : 1;

			DWORD	ReceiveWatchdogDisable : 1;		//	[4 ] 1 = disabled
													//		 0 = receive carriere longger than 2560 bytes are guaranteed to 
													//			 cause wdt counter to time out.
													//			 Packets shorter than 2048 bytes are guaranteed to pass.
		
			DWORD	ReceiveWatchdogRelease : 1;		//	[5 ] Time interval no carrier from receive watchdog expiration until
													//		 reenabling receive signal.
													//		 1 = 40 to 48 bit times from last carrier deassertion.
													//		 0 = 16 to 24 bit times from last carrier deassertion.

			DWORD	________Reserve__ : 2;			

			DWORD	________MUST_BE_ZERO_ : 1;		//	[8 ] !!! MUST BE ZERO !!!
		};

		DWORD	dwReg;
	};	

} 
CSR15_21140;


/* ------------------------------------------------------------------------------
 *
 *	CSR
 *
 * -------------------------------------------------------------------------------*/


typedef struct tagCSR 
{
	
	CSR0_21140		hwCSR0;		
	PAD(0,4);

	CSR_21140		hwCSR1;			//	Write only... Write with any value and 21140 checks for 
	PAD(1,4);						//		          frames to be transmitted.

	CSR_21140		hwCSR2;			//	Write only... Write with any value and 21140 checks for 
	PAD(2,4);						//		          receive descriptors to be acquired.

	CSR_21140		hwCSR3;			//	Write only... Descriptor List Address Register (Rx)	
	PAD(3,4);

	CSR_21140		hwCSR4;			//	Write only... Descriptor List Address Register (Tx)
	PAD(4,4);
	
	CSR5_21140		hwCSR5;	
	PAD(5,4);

	CSR6_21140		hwCSR6;	
	PAD(6,4);
	
	CSR7_21140		hwCSR7;	
	PAD(7,4);
	
	CSR8_21140		hwCSR8;	
	PAD(8,4);

	CSR9_21140		hwCSR9;		
	PAD(9,4);

	CSR10_21140		hwCSR10;
	PAD(a,4);
	
	CSR11_21140		hwCSR11;		
	PAD(b,4);


	CSR12_21140		hwCSR12;
	PAD(c,4);
#if 0                     //sudhakar
	DWORD			CSR_RESERVED_13;
	PAD(d,4);

	DWORD			CSR_RESERVED_14;
	PAD(e,4);
#endif
    CSR11_21140		hwCSR13;		
	PAD(d,4);


	CSR12_21140		hwCSR14;
	PAD(e,4);


	CSR15_21140		hwCSR15;	
	PAD(f,4);

} CSR, *PCSR;


/////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////////////////
//	RX RDES0
//

typedef	union _tagRxRdes0__
{
	struct
	{
		DWORD	zero : 1;						// [0 ]  Should always be zero.
		DWORD	CRCError : 1;					// [1 ]  CRC error occured in received frame also, when mii_err pin 
												//		 asserted.   Valid only when RDES0[8] = 1
		DWORD	DribblingBit : 1;				// [2 ]	 Frame contained noninteger multiple of 8 bits. Depends on RDES0[8]												
		DWORD	ReportOnMiiError : 1;			// [3 ]  rx error in physical layer was reported during frame reception.
		DWORD	ReceiveWatchdog : 1;			// [4 ]  1 = Rx watch dog timer expired while receiving current packet.
												//			 Valid when RDES0[8] set.
		DWORD	FrameType : 1;					// [5 ]  1 = Frame is ethernet type frame (frame length is > 1500 bytes).
												//		 0 = Frame is IEEE 802.3 frame.
												//			 Valid when RDES0[8] set.
		DWORD	CollisionSeen : 1;				// [6 ]  1 = Frame was damaged by collision (late collision).
												//			 Valid when RDES0[8] set.
		DWORD	FrameTooLong : 1;				// [7 ]  1 = Frame length > ethernet specified size (1518 bytes).
												//			 Valid when RDES0[8] set.
		DWORD	LastDescriptor :1;				// [8 ]  1 = Buffers pointed to by this descriptor are last buffers of frame.
		DWORD	FirstDescriptor : 1;			// [9 ]  1 = This descriptor contains the first buffer of a frame.
		DWORD	MulticastFrame : 1;				// [10]  1 = This frame has a multicast address.   Depends on RDES0[8]
		DWORD	RuntFrame : 1;					// [11]  1 = Frame was damaged by a collision.  
												//			 This will be set only if CSR6[3] is set.
												//			 Valid only when RDES0[8] set.
		DWORD	DataType : 2;					// [12]	 00 == Serial Receive Frame.		10 == External loop back.
												//		 01 == Internal Loop Back Frame.
		DWORD	DescriptorError : 1;			// [14]  1 = Frame truncation caused by a frame does not fit within the 
												//			 current descriptor buffer, and 21140 does not have access to
												//			 next descriptor.   Valid only when RDES0[8] set.
		DWORD	ErrorSummary : 1;				// [15]  Logical OR of RDES0[1, 6, 7, 11, 14]
		DWORD	FrameLength : 14;				// [16]	 Length (in bytes) of received frame including CRC.
												//	     Valid only when RDES0[8] is set and RDES[14] is reset.
		DWORD	FilteringFail : 1;				// [30]  Frame failed the address recognition filtering.
		DWORD	OwnBit : 1;						// [31]  When set 21140 owns the descriptor.   
												//		 Reset == host owns descriptor.   21140 clears this bit.
	};

	DWORD	dwReg;

} RX_RDES0;


/////////////////////////////////////////////////////////////////////////////////
//	RX RDES1
//

typedef union _tagRxRdes1__
{
	struct 
	{
		DWORD	Buffer1Size : 11;				// [0 ] Buffer size MUST BE multiple of 4
		DWORD	Buffer2Size : 11;				// [11] Buffer size MUST BE multiple of 4, not valid if RDES1[24] set.

		DWORD	________Reserve_ : 2;			

		DWORD	SecondAddressChained : 1;		// [24] 1 == Second address in the descriptor is the next descriptor addr.
												//		0 == Second address is second buffer of this descriptor.

		DWORD	ReceiveEndOfRing : 1;			// [25] 1 == Descriptor List reached its final descriptor.
	};

	DWORD	dwReg;

} RX_RDES1;


/* ------------------------------------------------------------------------------
 *
 *	RX RDES
 *
 * -------------------------------------------------------------------------------*/


typedef struct	_tagRxDescriptor__
{
	RX_RDES0	RDES0;		
	RX_RDES1	RDES1;
	DWORD		RDES2;		// Buffer address 1
	DWORD		RDES3;		// Buffer address 2

} RX_DESCRIPTOR_FORMAT, *PRX_DESCRIPTOR_FORMAT;



/////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////////////////
//	TX TDES0
//

typedef union _tagTxTdes0__
{
	struct
	{
		DWORD	Deferred : 1;					// [0 ] 1 == 21140 had to defer because carrier was asserted.
		DWORD	UnderFlow : 1;					// [1 ] 1 == Transmitter aborted message because data arrived late from
												//           memory.
		DWORD	LinkFailReport : 1;				// [2 ] 1 == Link test failed before frame was transmitted through symbol
												//		     port.   Valid only while using symbol mode CSR6[23] == 1
		DWORD	CollisionCount : 4;				// [3 ] # of collision b4 frame was transmitted.
		DWORD	HeartbeatFail : 1;				// [7 ] Effective only in 10Mbps.
		DWORD	ExcessiveCollision : 1;			// [8 ] Transmission was aborted after 16 successive collisions.
		DWORD	LateCollision : 1;				// [9 ] 1 == Late collision happened.
		DWORD	NoCarrier : 1;					// [10] 1 == Carrier signal from transceiver was not preset during 
												//           transmission.
		DWORD	LossOfCarrier : 1;				// [11] 1 == Loss of carrier during transmission.

		DWORD	________Reserved_ : 2;

		DWORD	TransmitJabberTimeout : 1;		// [14] 1 === Transmit jabber timer timed out.
		DWORD	ErrorSummary : 1;				// [15] Logical OR of TDES0[1, 8, 9, 10, 11, 14]

		DWORD	________Reserved__ : 15 ;		
		
		DWORD	OwnBit : 1;						// [31] 1 == Descriptor owned by 21140.

	};

	DWORD	dwReg;

} TX_TDES0;


/////////////////////////////////////////////////////////////////////////////////
//	TX TDES1
//

typedef union _tagTxTdes1__
{
	struct
	{
		DWORD	Buffer1Size : 11;				//	[0 ]	
		DWORD	Buffer2Size : 11;				//	[11]

		DWORD	FilteringType0: 1;				//  [22] FT0 and FT1 (TEDES1[28]) works together.

		DWORD	DisablePadding : 1;				//	[23] 1 == 21140 does not automatically add a padding field 
												//			  to < 64 bytes packet.
		DWORD	SecondAddressChained : 1;		//	[24] 1 == Second address is next descriptor rather than second buf addr
		DWORD	TransmitEndOfRing : 1;			//  [25]
		DWORD	AddCRCDisable : 1;				//	[26]
		DWORD	SetupPacket : 1;				//	[27] 1 == Indicates that the current descriptor is a setup frame descriptor.
		
		DWORD	FilteringType1: 1;				//	[28] Works together with TDES1[22]
		DWORD	FirstSegment : 1;				//	[29] 1 == Buffer contains first segment of a frame.
		DWORD	LastSegment : 1;				//	[30] 1 == Buffer contains last segment of a frame.
		DWORD	InterruptOnCompletion : 1;		//	[31] 1 == 21140 will set interrupt after this frame has been xmitted.
												//			  Valid only when TDES1[30] is set or it is a setup packet.

	};
	
	DWORD	dwReg;
} TX_TDES1;



/* ------------------------------------------------------------------------------
 *
 *	RX RDES
 *
 * -------------------------------------------------------------------------------*/


typedef struct	_tagTxDescriptor__
{
	TX_TDES0	TDES0;		
	TX_TDES1	TDES1;	
	DWORD		TDES2;		// Buffer address 1
	DWORD		TDES3;		// Buffer address 2
} TX_DESCRIPTOR_FORMAT, *PTX_DESCRIPTOR_FORMAT;


/////////////////////////////////////////////////////////////////////////////////
//	Defines for descriptors.
//


#define MAX_BUFFER_SIZE						1536						// 12*128(=max cache line size)
#define DESC_OWNED_BY_HOST					((ULONG)(0x7fffffff))
#define DESC_OWNED_BY_DEC21140				((ULONG)(0x80000000))
#define	SECOND_ADDRESS_CHAINED				(ULONG) (1 << 24)




/////////////////////////////////////////////////////////////////////////////////
//
//	Error returned from exported function...
//

#define	DEC21140_ERROR_TX_LOOPBACK		0x00000001	




/////////////////////////////////////////////////////////////////////////////////
//	Exported funtions to caller
//
//
BOOL	DEC21140Init (BYTE *pbBaseAddress, ULONG	dwMemOffset, USHORT MacAddr[3]);
void	DEC21140EnableInts (void);
void	DEC21140DisableInts (void);
DWORD	DEC21140GetPendingInts (void);
UINT16	DEC21140GetFrame (BYTE *pbData, UINT16 *pwLength/*, BOOL	bBootLoaderCall*/);
UINT16	DEC21140SendFrame (BYTE *pbData, DWORD dwLength);
void	DEC21140InitTxDescriptor (DWORD TxHead, DWORD TxBuffSize, BOOL bVirt);
void	DEC21140InitRxDescriptor (DWORD RxHead, DWORD RxBuffSize, BOOL bVirt);
DWORD	DEC21140QueryBufferSize (void);
DWORD	DEC21140QueryDescriptorSize (void);
                          
#endif 
// _DEC21140HARDWARE_