platform.h
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 882 行 · 第 1/3 页
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* Where in the memory map does PCI live?
* -------------------------------------------------------------------------------
* This represents a fairly liberal usage of address space. Even though the V3
* only has two windows (therefore we need to map stuff on the fly), we maintain
* the same addresses, even if they're not mapped.
*
*/
#define PHYS_PCI_MEM_BASE 0x40000000 /* 512 M */
#define PHYS_PCI_IO_BASE 0x60000000 /* 16M */
#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M */
#define PHYS_PCI_V3_BASE 0x62000000
#define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE
/* -------------------------------------------------------------------------------
* From AMBA UART (PL010) Block Specification (ARM-0001-CUST-DSPC-A03)
* -------------------------------------------------------------------------------
* UART Register Offsets.
*
*/
#define AMBA_UARTDR 0x00 /* Data read or written from the interface. */
#define AMBA_UARTRSR 0x04 /* Receive status register (Read). */
#define AMBA_UARTECR 0x04 /* Error clear register (Write). */
#define AMBA_UARTLCR_H 0x08 /* Line control register, high byte. */
#define AMBA_UARTLCR_M 0x0C /* Line control register, middle byte. */
#define AMBA_UARTLCR_L 0x10 /* Line control register, low byte. */
#define AMBA_UARTCR 0x14 /* Control register. */
#define AMBA_UARTFR 0x18 /* Flag register (Read only). */
#define AMBA_UARTIIR 0x1C /* Interrupt indentification register (Read). */
#define AMBA_UARTICR 0x1C /* Interrupt clear register (Write). */
#define AMBA_UARTILPR 0x20 /* IrDA low power counter register. */
#define AMBA_UARTRSR_OE 0x08
#define AMBA_UARTRSR_BE 0x04
#define AMBA_UARTRSR_PE 0x02
#define AMBA_UARTRSR_FE 0x01
#define AMBA_UARTFR_TXFE 0x80
#define AMBA_UARTFR_RXFF 0x40
#define AMBA_UARTFR_TXFF 0x20
#define AMBA_UARTFR_RXFE 0x10
#define AMBA_UARTFR_BUSY 0x08
#define AMBA_UARTFR_TMSK (AMBA_UARTFR_TXFF + AMBA_UARTFR_BUSY)
#define AMBA_UARTFR_DCD 0x04
#define AMBA_UARTFR_DSR 0x02
#define AMBA_UARTFR_CTS 0x01
#define AMBA_UARTCR_RTIE 0x40
#define AMBA_UARTCR_TIE 0x20
#define AMBA_UARTCR_RIE 0x10
#define AMBA_UARTCR_MSIE 0x08
#define AMBA_UARTCR_IIRLP 0x04
#define AMBA_UARTCR_SIREN 0x02
#define AMBA_UARTCR_UARTEN 0x01
#define AMBA_UARTLCR_H_WLEN_8 0x60
#define AMBA_UARTLCR_H_WLEN_7 0x40
#define AMBA_UARTLCR_H_WLEN_6 0x20
#define AMBA_UARTLCR_H_WLEN_5 0x00
#define AMBA_UARTLCR_H_FEN 0x10
#define AMBA_UARTLCR_H_STP2 0x08
#define AMBA_UARTLCR_H_EPS 0x04
#define AMBA_UARTLCR_H_PEN 0x02
#define AMBA_UARTLCR_H_BRK 0x01
#define AMBA_UARTIIR_RTIS 0x08
#define AMBA_UARTIIR_TIS 0x04
#define AMBA_UARTIIR_RIS 0x02
#define AMBA_UARTIIR_MIS 0x01
#define AMBA_UARTIIR_MASK 0x0F
#define AMBA_UART_BSIZE_MASK 0x9F
#define AMBA_UART_PARITY_MASK 0xF9
#define AMBA_UART_SBIT_MASK 0xF7
#define ARM_BAUD_460800 1
#define ARM_BAUD_230400 3
#define ARM_BAUD_115200 7
#define ARM_BAUD_57600 15
#define ARM_BAUD_38400 23
#define ARM_BAUD_19200 47
#define ARM_BAUD_14400 63
#define ARM_BAUD_9600 95
#define ARM_BAUD_4800 191
#define ARM_BAUD_2400 383
#define ARM_BAUD_1200 767
/* ===============================================================================
* Start of uHAL definitions
* ===============================================================================
* -------------------------------------------------------------------------------
* LED's - uHAL will not touch the LED on the header card.
* -------------------------------------------------------------------------------
*
*/
#define uHAL_LED_ON 1
#define uHAL_LED_OFF 0
#define uHAL_NUM_OF_LEDS 4
#define GREEN_LED 0x01
#define YELLOW_LED 0x02
#define RED_LED 0x04
#define GREEN_LED_2 0x08
#define ALL_LEDS 0x0F
#define LED_BANK INTEGRATOR_DBG_LEDS
#define uHAL_LED_MASKS {0, GREEN_LED, YELLOW_LED, RED_LED, GREEN_LED_2}
#define uHAL_LED_OFFSETS {0, (void *)LED_BANK, (void *)LED_BANK, (void *)LED_BANK, (void *)LED_BANK}
/*
* Memory definitions - run uHAL out of SSRAM.
*
*/
#define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE
/*
* Application Flash
*
*/
#define FLASH_BASE INTEGRATOR_FLASH_BASE
#define FLASH_SIZE INTEGRATOR_FLASH_SIZE
#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
#define FLASH_BLOCK_SIZE SZ_128K
/*
* Boot Flash
*
*/
#define EPROM_BASE INTEGRATOR_BOOT_ROM_HI
#define EPROM_SIZE INTEGRATOR_BOOT_ROM_SIZE
#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
/*
* Clean base - dummy
*
*/
#define CLEAN_BASE EPROM_BASE
/*
* UART definitions
*
*/
/*
* Which com port can the OS use?
*
*/
/* Default port to talk to host (via debugger) */
#define HOST_COMPORT INTEGRATOR_UART0_BASE
#define HOST_IRQBIT_NUMBER IRQ_UARTINT0
#define HOST_IRQBIT_MASK IRQMASK_UARTINT0
#define HOST_IRQBIT HOST_IRQBIT_MASK
/* Default port for use by Operating System or program */
#define OS_COMPORT INTEGRATOR_UART0_BASE
#define OS_IRQBIT_NUMBER IRQ_UARTINT0
#define OS_IRQBIT_MASK IRQMASK_UARTINT0
#define OS_IRQBIT OS_IRQBIT_MASK
#define DEBUG_COMPORT OS_COMPORT
#define DEBUG_IRQBIT OS_IRQBIT
/* Values to set given baud rates */
#define DEFAULT_HOST_BAUD ARM_BAUD_9600
#define DEFAULT_OS_BAUD ARM_BAUD_38400
#define GET_STATUS(p) (inb( (void *) ((p) + AMBA_UARTFR) ) & 0xFF)
#define GET_CHAR(p) (inb( (void *) ((p) + AMBA_UARTDR) ))
#define PUT_CHAR(p, c) (outb(c, (void *)((p) + AMBA_UARTDR)))
#define IO_READ(p) (*(volatile unsigned char *)(p))
#define IO_WRITE(p, c) (*(volatile unsigned char *)(p) = \
(unsigned char)(c))
#define RX_DATA(s) (((s) & AMBA_UARTFR_RXFE) == 0)
#define TX_READY(s) (((s) & AMBA_UARTFR_TXFF) == 0)
#define TX_EMPTY(p) ((GET_STATUS(p) & AMBA_UARTFR_TMSK) == 0)
/*
* Timer definitions
*
* Only use timer 1 & 2
* (both run at 24MHz and will need the clock divider set to 16).
*
* Timer 0 runs at bus frequency and therefore could vary and currently
* uHAL can't handle that.
*
*/
#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
#define MAX_TIMER 2
#define MAX_PERIOD 699050
#define TICKS_PER_uSEC 24
/* Interrupt Flags */
#define SEMIHOSTED_INTS 0
/*
* These are useconds NOT ticks.
*
*/
#define mSEC_1 1000
#define mSEC_5 (mSEC_1 * 5)
#define mSEC_10 (mSEC_1 * 10)
#define mSEC_25 (mSEC_1 * 25)
#define SEC_1 (mSEC_1 * 1000)
#define OS_TIMER 1
#define OS_TIMERINT IRQ_TIMERINT1
#define HOST_TIMER MAX_TIMER
/* Timer definitions.
* The irq numbers of the individual timers
*/
#define TIMER_VECTORS { 0, IRQ_TIMERINT1, IRQ_TIMERINT2}
/*
*/
/* Number of Level2 table entries in uHAL_AddressTable
*/
#define L2_TABLE_ENTRIES 1
/* macros to map from PCI memory/IO addresses to local bus addresses */
#define _MapAddress(a) (a)
#define _MapIOAddress ((U32)UHAL_PCI_IO + (U32)(a))
#define _MapMemAddress(a) (a)
#define ALLBITS 0xffffffff
#define INTEGRATOR_CSR_BASE 0x10000000
#define INTEGRATOR_CSR_SIZE 0x10000000
/* Purely for compatability with SEMIHOSTED (defined in uart.h in uHAL):
*/
#define InterruptId 2
/* Purely for compatability with uHAL (defined in superio_h.s in SEMIHOSTED):
*/
#define EnableInt 0x04
#define CntlModem 0x10
#ifdef uHAL_HEAP
#ifdef USE_C_LIBRARY
#define uHAL_HEAP_BASE (INTEGRATOR_SSRAM_BASE + SZ_1M)
#define uHAL_HEAP_SIZE (SZ_32M - SZ_1M - SZ_1M - 4)
#define uHAL_STACK_BASE SZ_32M
#define uHAL_STACK_SIZE SZ_1M
#else
#define uHAL_HEAP_BASE (INTEGRATOR_SSRAM_BASE + INTEGRATOR_SSRAM_SIZE - SZ_64K)
#define uHAL_HEAP_SIZE SZ_16K
#define uHAL_STACK_SIZE SZ_16K
#define uHAL_STACK_BASE (uHAL_HEAP_BASE + SZ32K)
#endif
#endif
/* -------------------------------------------------------------------------------
*/
/* Flash Library required macros to enable/disable flash writes */
#define FL_SC_CONTROL 0x06
#define INTEL_FL_WRITE_EN {unsigned int temp= *(volatile unsigned int *)INTEGRATOR_EBI_CSR1;temp |=INTEGRATOR_EBI_WRITE_ENABLE;*(volatile unsigned int *)INTEGRATOR_EBI_CSR1 = temp;*(volatile unsigned int *)INTEGRATOR_SC_CTRLS = FL_SC_CONTROL;}
#define INTEL_FL_WRITE_DIS {unsigned int temp= *(volatile unsigned int *)INTEGRATOR_EBI_CSR1;temp &=~INTEGRATOR_EBI_WRITE_ENABLE;*(volatile unsigned int *)INTEGRATOR_EBI_CSR1 = temp;*(volatile unsigned int *)INTEGRATOR_SC_CTRLS = FL_SC_CONTROL;}
#define ATMEL_FL_WRITE_EN {unsigned int temp= *(volatile unsigned int *)INTEGRATOR_EBI_CSR0;temp |=INTEGRATOR_EBI_WRITE_ENABLE;*(volatile unsigned int *)INTEGRATOR_EBI_CSR0 = temp;*(volatile unsigned int *)INTEGRATOR_SC_CTRLS = FL_SC_CONTROL;}
#define ATMEL_FL_WRITE_DIS {unsigned int temp= *(volatile unsigned int *)INTEGRATOR_EBI_CSR0;temp &=~INTEGRATOR_EBI_WRITE_ENABLE;*(volatile unsigned int *)INTEGRATOR_EBI_CSR0 = temp;*(volatile unsigned int *)INTEGRATOR_SC_CTRLS = FL_SC_CONTROL;}
/* -------------------------------------------------------------------------------
*/
// IDSELs.
#define PCI_SLOT1 0xC // J9
#define PCI_SLOT2 0xB // J10
#define PCI_SLOT3 0xA // J11
#define EDBG_MEMORY_START (0x88050000)
#define EDBG_MEMORY_SIZE (0x00020000)
#endif
/* END */
/* EOF platform.? */
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