platform.h
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 882 行 · 第 1/3 页
H
882 行
#define IRQ_RAW_STATUS 0x04
#define IRQ_ENABLE 0x08
#define IRQ_ENABLE_SET 0x08
#define IRQ_ENABLE_CLEAR 0x0C
#define IRQ_SOFT_SET 0x10
#define IRQ_SOFT_CLEAR 0x14
#define FIQ_STATUS 0x20
#define FIQ_RAW_STATUS 0x24
#define FIQ_ENABLE 0x28
#define FIQ_ENABLE_SET 0x28
#define FIQ_ENABLE_CLEAR 0x2C
/*
* Interrupt numbers
*
*/
#define IRQ_SOFTINT 0
#define IRQ_UARTINT0 1
#define IRQ_UARTINT1 2
#define IRQ_KMIINT0 3
#define IRQ_KMIINT1 4
#define IRQ_TIMERINT0 5
#define IRQ_TIMERINT1 6
#define IRQ_TIMERINT2 7
#define IRQ_RTCINT 8
#define IRQ_EXPINT0 9
#define IRQ_EXPINT1 10
#define IRQ_EXPINT2 11
#define IRQ_EXPINT3 12
#define IRQ_PCIINT0 13 // PCI INTA
#define IRQ_PCIINT1 14 // PCI INTB
#define IRQ_PCIINT2 15 // PCI INTC
#define IRQ_PCIINT3 16 // PCI INTD
#define IRQ_V3INT 17
#define IRQ_CPINT0 18
#define IRQ_CPINT1 19
#define IRQ_LBUSTIMEOUT 20
#define IRQ_APCINT 21
/*
* Interrupt bit positions
*
*/
#define IRQMASK_SOFTINT BIT0
#define IRQMASK_UARTINT0 BIT1
#define IRQMASK_UARTINT1 BIT2
#define IRQMASK_KMIINT0 BIT3
#define IRQMASK_KMIINT1 BIT4
#define IRQMASK_TIMERINT0 BIT5
#define IRQMASK_TIMERINT1 BIT6
#define IRQMASK_TIMERINT2 BIT7
#define IRQMASK_RTCINT BIT8
#define IRQMASK_EXPINT0 BIT9
#define IRQMASK_EXPINT1 BIT10
#define IRQMASK_EXPINT2 BIT11
#define IRQMASK_EXPINT3 BIT12
#define IRQMASK_PCIINT0 BIT13
#define IRQMASK_PCIINT1 BIT14
#define IRQMASK_PCIINT2 BIT15
#define IRQMASK_PCIINT3 BIT16
#define IRQMASK_V3INT BIT17
#define IRQMASK_CPINT0 BIT18
#define IRQMASK_CPINT1 BIT19
#define IRQMASK_LBUSTIMEOUT BIT20
#define IRQMASK_APCINT BIT21
#define IRQMASK_ALL 0x3FFFFF
#define IRQ_KEYBDINT IRQ_KMIINT0
#define IRQ_MOUSEINT IRQ_KMIINT1
#define IRQMASK_KEYBDINT IRQMASK_KMIINT0
#define IRQMASK_MOUSEINT IRQMASK_KMIINT1
/*
* FIQ interrupts definitions are the same the IRQ definitions.
*
*/
#define FIQ_SOFTINT IRQ_SOFTINT
#define FIQ_UARTINT0 IRQ_UARTINT0
#define FIQ_UARTINT1 IRQ_UARTINT1
#define FIQ_KMIINT0 IRQ_KMIINT0
#define FIQ_KMIINT1 IRQ_KMIINT1
#define FIQ_TIMERINT0 IRQ_TIMERINT0
#define FIQ_TIMERINT1 IRQ_TIMERINT1
#define FIQ_TIMERINT2 IRQ_TIMERINT2
#define FIQ_RTCINT IRQ_RTCINT
#define FIQ_EXPINT0 IRQ_EXPINT0
#define FIQ_EXPINT1 IRQ_EXPINT1
#define FIQ_EXPINT2 IRQ_EXPINT2
#define FIQ_EXPINT3 IRQ_EXPINT3
#define FIQ_PCIINT0 IRQ_PCIINT0
#define FIQ_PCIINT1 IRQ_PCIINT1
#define FIQ_PCIINT2 IRQ_PCIINT2
#define FIQ_PCIINT3 IRQ_PCIINT3
#define FIQ_V3INT IRQ_V3INT
#define FIQ_CPINT0 IRQ_CPINT0
#define FIQ_CPINT1 IRQ_CPINT1
#define FIQ_LBUSTIMEOUT IRQ_LBUSTIMEOUT
#define FIQ_APCINT IRQ_APCINT
#define FIQMASK_SOFTINT IRQMASK_SOFTINT
#define FIQMASK_UARTINT0 IRQMASK_UARTINT0
#define FIQMASK_UARTINT1 IRQMASK_UARTINT1
#define FIQMASK_KMIINT0 IRQMASK_KMIINT0
#define FIQMASK_KMIINT1 IRQMASK_KMIINT1
#define FIQMASK_TIMERINT0 IRQMASK_TIMERINT0
#define FIQMASK_TIMERINT1 IRQMASK_TIMERINT1
#define FIQMASK_TIMERINT2 IRQMASK_TIMERINT2
#define FIQMASK_RTCINT IRQMASK_RTCINT
#define FIQMASK_EXPINT0 IRQMASK_EXPINT0
#define FIQMASK_EXPINT1 IRQMASK_EXPINT1
#define FIQMASK_EXPINT2 IRQMASK_EXPINT2
#define FIQMASK_EXPINT3 IRQMASK_EXPINT3
#define FIQMASK_PCIINT0 IRQMASK_PCIINT0
#define FIQMASK_PCIINT1 IRQMASK_PCIINT1
#define FIQMASK_PCIINT2 IRQMASK_PCIINT2
#define FIQMASK_PCIINT3 IRQMASK_PCIINT3
#define FIQMASK_V3INT IRQMASK_V3INT
#define FIQMASK_CPINT0 IRQMASK_CPINT0
#define FIQMASK_CPINT1 IRQMASK_CPINT1
#define FIQMASK_LBUSTIMEOUT IRQMASK_LBUSTIMEOUT
#define FIQMASK_APCINT IRQMASK_APCINT
#define FIQMASK_ALL IRQMASK_ALL
#define FIQ_KEYBDINT IRQ_KEYBDINT
#define FIQ_MOUSEINT IRQ_MOUSEINT
#define FIQMASK_KEYBDINT IRQMASK_KEYBDINT
#define FIQMASK_MOUSEINT IRQMASK_MOUSEINT
#define MAXIRQNUM 21
#define MAXFIQNUM 21
#define MAXSWINUM 31
#define NR_IRQS (MAXIRQNUM + 1)
/* -------------------------------------------------------------------------------
* KMI keyboard/mouse definitions
* -------------------------------------------------------------------------------
*/
/* PS2 Keyboard interface */
#define KMI0_BASE INTEGRATOR_KBD_BASE
#define KEYB_CR (INTEGRATOR_KBD_BASE)
#define KEYB_STAT (INTEGRATOR_KBD_BASE + 0x4)
#define KEYB_DATA (INTEGRATOR_KBD_BASE + 0x8)
#define KEYB_CLK (INTEGRATOR_KBD_BASE + 0xC)
/* PS2 Mouse interface */
#define KMI1_BASE INTEGRATOR_MOUSE_BASE
#define MOUSE_CR INTEGRATOR_MOUSE_BASE
#define MOUSE_STAT (INTEGRATOR_MOUSE_BASE+0x4)
#define MOUSE_DATA (INTEGRATOR_MOUSE_BASE+0x8)
#define MOUSE_CLK (INTEGRATOR_MOUSE_BASE+0xC)
/* general KMI register macros */
#define KMI_CR(b) ((volatile unsigned int *)b)
#define KMI_STAT(b) ((volatile unsigned int *)(b+0x4))
#define KMI_DATA(b) ((volatile unsigned int *)(b+0x8))
#define KMI_CLK(b) ((volatile unsigned int *)(b+0xC))
/* KMI constants */
#define KMI_TXEMPTY 0x40
#define KMI_TXBUSY 0x20
#define KMI_RXFULL 0x10
#define KMI_RXBUSY 0x08
#define KMI_PARITY 0x04
/* -------------------------------------------------------------------------------
* V3 Local Bus to PCI Bridge definitions
* -------------------------------------------------------------------------------
* Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
* All V3 register names are prefaced by V3_ to avoid clashing with any other
* PCI definitions. Their names match the user's manual.
*
* I'm assuming that I20 is disabled.
*
*/
#define V3_PCI_VENDOR 0x00000000
#define V3_PCI_DEVICE 0x00000002
#define V3_PCI_CMD 0x00000004
#define V3_PCI_STAT 0x00000006
#define V3_PCI_CC_REV 0x00000008
#define V3_PCI_HDR_CFG 0x0000000C
#define V3_PCI_IO_BASE 0x00000010
#define V3_PCI_BASE0 0x00000014
#define V3_PCI_BASE1 0x00000018
#define V3_PCI_SUB_VENDOR 0x0000002C
#define V3_PCI_SUB_ID 0x0000002E
#define V3_PCI_ROM 0x00000030
#define V3_PCI_BPARAM 0x0000003C
#define V3_PCI_MAP0 0x00000040
#define V3_PCI_MAP1 0x00000044
#define V3_PCI_INT_STAT 0x00000048
#define V3_PCI_INT_CFG 0x0000004C
#define V3_LB_BASE0 0x00000054
#define V3_LB_BASE1 0x00000058
#define V3_LB_MAP0 0x0000005E
#define V3_LB_MAP1 0x00000062
#define V3_LB_BASE2 0x00000064
#define V3_LB_MAP2 0x00000066
#define V3_LB_SIZE 0x00000068
#define V3_LB_IO_BASE 0x0000006E
#define V3_FIFO_CFG 0x00000070
#define V3_FIFO_PRIORITY 0x00000072
#define V3_FIFO_STAT 0x00000074
#define V3_LB_ISTAT 0x00000076
#define V3_LB_IMASK 0x00000077
#define V3_SYSTEM 0x00000078
#define V3_LB_CFG 0x0000007A
#define V3_PCI_CFG 0x0000007C
#define V3_DMA_PCI_ADR0 0x00000080
#define V3_DMA_PCI_ADR1 0x00000090
#define V3_DMA_LOCAL_ADR0 0x00000084
#define V3_DMA_LOCAL_ADR1 0x00000094
#define V3_DMA_LENGTH0 0x00000088
#define V3_DMA_LENGTH1 0x00000098
#define V3_DMA_CSR0 0x0000008B
#define V3_DMA_CSR1 0x0000009B
#define V3_DMA_CTLB_ADR0 0x0000008C
#define V3_DMA_CTLB_ADR1 0x0000009C
#define V3_DMA_DELAY 0x000000E0
#define V3_MAIL_DATA 0x000000C0
#define V3_PCI_MAIL_IEWR 0x000000D0
#define V3_PCI_MAIL_IERD 0x000000D2
#define V3_LB_MAIL_IEWR 0x000000D4
#define V3_LB_MAIL_IERD 0x000000D6
#define V3_MAIL_WR_STAT 0x000000D8
#define V3_MAIL_RD_STAT 0x000000DA
#define V3_QBA_MAP 0x000000DC
/* PCI COMMAND REGISTER bits
*/
#define V3_COMMAND_M_FBB_EN BIT9
#define V3_COMMAND_M_SERR_EN BIT8
#define V3_COMMAND_M_PAR_EN BIT6
#define V3_COMMAND_M_MASTER_EN BIT2
#define V3_COMMAND_M_MEM_EN BIT1
#define V3_COMMAND_M_IO_EN BIT0
/* SYSTEM REGISTER bits
*/
#define V3_SYSTEM_M_RST_OUT BIT15
#define V3_SYSTEM_M_LOCK BIT14
/* PCI_CFG bits
*/
#define V3_PCI_CFG_M_RETRY_EN BIT10
#define V3_PCI_CFG_M_AD_LOW1 BIT9
#define V3_PCI_CFG_M_AD_LOW0 BIT8
/* PCI_BASE register bits (PCI -> Local Bus)
*/
#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
#define V3_PCI_BASE_M_PREFETCH BIT3
#define V3_PCI_BASE_M_TYPE BIT2+BIT1
#define V3_PCI_BASE_M_IO BIT0
/* PCI MAP register bits (PCI -> Local bus)
*/
#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
#define V3_PCI_MAP_M_RD_POST_INH BIT15
#define V3_PCI_MAP_M_ROM_SIZE BIT11+BIT10
#define V3_PCI_MAP_M_SWAP BIT9+BIT8
#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
#define V3_PCI_MAP_M_REG_EN BIT1
#define V3_PCI_MAP_M_ENABLE BIT0
/* 9 => 512M window size
*/
#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090
/* A => 1024M window size
*/
#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0
/* LB_BASE register bits (Local bus -> PCI)
*/
#define V3_LB_BASE_M_MAP_ADR 0xFFF00000
#define V3_LB_BASE_M_SWAP BIT9+BIT8
#define V3_LB_BASE_M_ADR_SIZE 0x000000F0
#define V3_LB_BASE_M_PREFETCH BIT3
#define V3_LB_BASE_M_ENABLE BIT0
/* LB_MAP register bits (Local bus -> PCI)
*/
#define V3_LB_MAP_M_MAP_ADR 0xFFF0
#define V3_LB_MAP_M_TYPE 0x000E
#define V3_LB_MAP_M_AD_LOW_EN BIT0
/* -------------------------------------------------------------------------------
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?