mqhw2.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 1,060 行 · 第 1/4 页

/* $Header: /Windows CE/BigSur/SDBTEST/MediaQ/mqhw2.h 1     6/20/00 5:29p Mrastogi $
 * 
 * Copyright (c) 1999 by MediaQ, Incorporated.
 * All Rights Reserved.
 *
 * Confidential and Proprietary to MediaQ, Incorporated.
 *
 * MQHW2.H : Main header file for MediaQ LCD/CRT Graphics Controller and
 *		 	 2D engine.
 *
 * $Log: /Windows CE/BigSur/SDBTEST/MediaQ/mqhw2.h $
 * 
 * 1     6/20/00 5:29p Mrastogi
 * Base Version received from HCL Noida on June 07, 2000.
// 
// 1     9/15/99 10:33a Ngupta
 * 
 *    Rev 1.16   Aug 16 1999 19:06:50   hoang
 * For TOS_MIPS, changed FB_BASE = 6d800000
 * 
 *    Rev 1.15   Aug 11 1999 11:22:42   chijen
 * add MIP_NEC register base
 * 
 *    Rev 1.14   Aug 05 1999 09:26:34   tzyywei
 * Add Toshiba Pallas support
 * 
 *    Rev 1.13   Jul 09 1999 10:59:46   benny
 * Disable PAGE_PHYSICAL mapping for SA BOARDS by adding DEVMAP macro.
 * 
 *    Rev 1.12   Jul 06 1999 14:22:08   tzyywei
 * define CEPC  if x86 platform is defined.
 * 
 *    Rev 1.11   Jun 30 1999 15:43:42   benny
 * Changes made to Enable PCI code.
 * 
 *    Rev 1.10   Jun 23 1999 16:07:44   chijen
 * update new bit definition for rev1A
 * 
 *    Rev 1.9   Jun 15 1999 10:32:40   chijen
 * move REV_?? to sources if to build REV_0C or earlier silicon
 * 
 *    Rev 1.8   May 28 1999 15:43:38   benny
 * Turned on RectFill24 and modify WAITCMDFIFO() macro and
 * ALWAYS_SET_STRIDE macro.
 * 
 *    Rev 1.7   May 14 1999 11:43:06   yuhuan
 * Re-organize.
 * 
 *    Rev 1.6   Apr 29 1999 17:31:34   yuhuan
 * Some new constants
 * 
 *    Rev 1.5   Apr 07 1999 10:42:02   chijen
 * fix comment
 * 
 *    Rev 1.4   Apr 07 1999 10:39:28   chijen
 * add intREG and fix palREG
 * 
 *    Rev 1.3   Apr 04 1999 17:52:54   chijen
 * fix sa fb_base
 * 
 *    Rev 1.2   Mar 30 1999 16:20:28   tzyywei
 * update for JP demo.
 * 
 *    Rev 1.1   Feb 24 1999 13:02:26   tzyywei
 * fixed typo for MIPS platform
 * 
 *    Rev 1.0   Feb 20 1999 21:32:12   yuhuan
 * Initial revision.
 */

#ifndef __MQHW2_H__
#define __MQHW2_H__

#ifdef MIPS
#if defined(R4100) || defined(R4111) || defined(R4200) || defined(R4300)
#define	MIPS_NEC
#elif defined(R3000)
#define	MIPS_TOS
#endif
#endif

#ifdef x86
#define CEPC
#endif

#ifdef SA1100
#define	STRONG_ARM
#define  DEVMAP(x) if(1)
#else
#define  DEVMAP(x) x
#endif

// Chip Revision - moved to sources
//#define	REV_A
//#define	REV_B
//#define		REV_C
//#define		REV_0X

#ifdef	REV_0X
#define	ALWAYS_SET_DEST_STRIDE				//See comments in mqtables.h
#endif

// Equates for chip debuggging and bug
//
#define NO_WAIT_PowerSeqOff

#define uBUSW					4			// processor bus width
#define MQ200_DEVICE			0x02004D51	// device=0x0100, vendor=0x0000
#define PM_ID_CAP				0x06210001	// Power management ID/capability

// Generic typedef
//
#ifdef _USE_MQEMUL

#include "mqemul.h"
#undef  uBUSW
#define uBUSW					1			// # of dword

#define SRC_IMAGE_DATA			(0x20 * uBUSW)  // Source Data register for GE

#if ETARGET == IS_WINSDK
#define	geINIT( psurf )			EmulGeInit()
#else	//IS_WINSDK
#define	geINIT( psurf ) 		EmulGeInit( \
			 						((LPVOID)((DWORD)(psurf->Buffer()) - \
									((DWORD)(psurf->OffsetInVideoMemory())))), \
			 						psurf->Stride(), \
			 						EGPEFormatToBpp[psurf->Format()] )
#endif	//IS_WINSDK
#define geREG( id, data )		EmulGeReg( id, data )
#define	geTERMINATE()			EmulGeTerminate();
#define	geWAITSRCFIFO( cnt )	EmulGeWaitSrcFIFO( cnt / 2 )
#define	geWAITCMDFIFO( cnt )	EmulGeWaitCmdFIFO( cnt )
#define	geWAITFULLCMDFIFO		EmulGeWaitCmdFIFO( 16 )

#define	GPE_ZONE_MQEMUL1		DEBUGZONE(14)
#define	GPE_ZONE_MQEMUL2		DEBUGZONE(15)

#else	//_USE_MQEMUL

#define SRC_IMAGE_DATA			(0x3000 * uBUSW)  // Source Data register for GE

#define CHECK_GE_NOTBUSY

#define geINIT( psurf ) 
#define	geTERMINATE()
#ifdef CHECK_GE_NOTBUSY
#define	geWAITNOTBUSY			WaitGENotBusy()
#else
#define	geWAITNOTBUSY
#endif	//CHECK_GE_NOTBUSY
#ifdef CHECK_SRCFIFO
#define	geWAITSRCFIFO( cnt )	WaitSrcFIFO( cnt )
#else
#define	geWAITSRCFIFO( cnt )
#endif	//CHECK_SRCFIFO
#ifdef CHECK_CMDFIFO
#define	geWAITFULLCMDFIFO		WaitCmdFIFO( 16 )
//TMP MOVED BACK TO MQUTILS.BLT ==> BEN 5/28/99
//#ifdef ALWAYS_SET_DEST_STRIDE
//#define	geWAITCMDFIFO( cnt )	WaitCmdFIFO( (cnt + 1) )
//#else
#define	geWAITCMDFIFO( cnt )	WaitCmdFIFO( cnt )
//#endif	//ALWAYS_SET_DEST_STRIDE
#else	//CHECK_CMDFIFO
#define	geWAITFULLCMDFIFO
#define	geWAITCMDFIFO( cnt )
#endif	//CHECK_CMDFIFO

#endif	//_USE_MQEMUL

#define REG32(base, id)			(*((PULONG)(m_pMMIO+(base)+(id))))
#define REG32_PAL(base, idx)	(*((PULONG)(m_pMMIO+(base)+((idx)*uBUSW))))
#define REG32X_PAL(mmio, idx)	(*((PULONG)(mmio+((idx)*uBUSW))))

// Memory-mapped base address
//
#ifdef	SHx
#define FB_BASE				0x93800000L		// frame buffer - for sh3/4
#elif defined( MIPS_NEC )
#define FB_BASE				0xAA000000L		// frame buffer - for NEC MIPS
#define IOREGS_BASE			0xAB000000L		// IO register base - for NEC MIPS
#define IOREGS_SIZE			0x00001000L		// IO register size
#elif defined( MIPS_TOS )
// #define FB_BASE				0x6F800000L		// frame buffer - for Toshiba MIPS
#define FB_BASE				0x6D800000L		// frame buffer - for Toshiba MIPS
#elif defined( STRONG_ARM )
#define FB_BASE				0xb8400000L		// frame buffer - for StrongARM
#elif defined( CEPC )
#define FB_BASE				0xff400000L		// frame buffer - for PCI on CEPC
#elif defined( SC400 )
#define FB_BASE				0xff400000L		// frame buffer - for PCI on AMD486
#endif

#ifdef CEPC
#define MMIO_BASE			0xff800000L
#elif defined( SC400 )
#define MMIO_BASE			0xff800000L
#else
#define MMIO_BASE	  		(FB_BASE + 0x600000L)
#endif
#define M_SIZE				0x00002000L 	// Size of each MQ module (8KB)

// MQ200 module offset
//
#define PM_BASE				0					// Power Management + Clk Gen
#define CC_BASE				(PM_BASE+M_SIZE)	// CPU interface
#define MM_BASE				(CC_BASE+M_SIZE)	// Memory Controller (m1/m2)
#define VI_BASE				(MM_BASE+M_SIZE)	// Video-in controller
#define IN_BASE				(VI_BASE+M_SIZE)	// Interrupt controller
#define GC_BASE				(IN_BASE+M_SIZE)	// Graphics Controller 1/2
#define GE_BASE				(GC_BASE+M_SIZE)	// Graphics engine
#define FP_BASE				(GE_BASE+M_SIZE)	// Flat panel interface
#define C1_BASE				(FP_BASE+M_SIZE)	// Color palette 1
#define C2_BASE				(C1_BASE+M_SIZE)	// Color palette 2
#define DC_BASE				(C2_BASE+M_SIZE)	// Device Configuration Space
#define PC_BASE				(DC_BASE+M_SIZE)	// PCI Configuration Header
#define PSF_BASE			(PC_BASE+M_SIZE)	// Primary Source FIFO Space
#define SSF_BASE			(PSF_BASE+M_SIZE)	// Secondary Source FIFO Space
#define LAST_BASE			(PSF_BASE+M_SIZE)	// First byte outside of MMIO

#define GE2_BASE			(GE_BASE+0x200 )	// Graphics engine (GE2)

#define MMIO_SIZE			(LAST_BASE - PM_BASE)	// memory-mapped size
#define FB_SIZE				0x200000L				// 2MB memory
#define LAST_ADDR          	0x200000L
#define LAST_KB				1024
#define GC_OFFSET			0x80

#ifdef _USE_MQEMUL
#define geREG( id, data )	EmulGeReg( id, data )
#define geRREG( id )
#define gcREG( id, data )	EmulGcReg( id, data )
#define gcRREG( id )
#else
// Init and GE emulation are two different aminals
#ifdef _EMUL_MQINIT
#define geREG(id,data)    	EmulgeREG(id,data)
#define geRREG(id)        	EmulgeREAD(id)
#else
	#ifndef	GE_OPTIMIZE_1
		#ifdef DDIDUMP
		#define geREG(id, data)     (REG32(GE2_BASE,id) = data)
		#define geRREG( id )  		(REG32(GE2_BASE,id))
		#else	// DDI
		#define geREG(id, data)     (REG32(GE_BASE,id) = data)
		#define geRREG( id )  		(REG32(GE_BASE,id))
		#endif //DDIDUMP
	#else
	#define geREG(id, data)     (REG32(GE_BASE,id) = data)
	#define geRREG( id )  		(REG32(GE_BASE,id))
	#endif
//#define	gcREG(id, data)	(REG32(GC_BASE,id) = data)
#define	gcRREG( id )		(REG32(GC_BASE,id))
#endif 	// _EMUL_MQINIT
#endif	//_USE_MQEMUL

#ifdef _EMUL_MQINIT
// Register buffer declaration
//
#undef uBUSW
#define uBUSW					1		// # of dword
#include "emulinit.h"
#define gc1REG(id,data)			Emulgc1REG(id,data)
#define gc1READ(id)				Emulgc1READ(id)