mqhw2.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 1,060 行 · 第 1/4 页

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#define gc2REG(id,data)			Emulgc2REG(id,data)
#define gc2READ(id)				Emulgc2READ(id)
#define fpREG(id,data)			EmulfpREG(id,data)
#define fpREAD(id)				EmulfpREAD(id)
#define g1pREG(idx,data)		Emulg1pREG(idx,data)
#define g1pREAD(idx)			Emulg1pREAD(idx)
#define g2pREG(idx,data)		Emulg2pREG(idx,data)
#define g2pREAD(idx)			Emulg1pREAD(idx)
#define palREG(idx,data)
#define palREAD(idx)
#define dcREG(id,data)    		EmuldcREG(id,data)
#define dcREAD(id)				EmuldcREAD(id)
#define pmuREG(id,data)    		EmulpmuREG(id,data)
#define pmuREAD(id)				EmulpmuREAD(id)
#define pciREG(id,data)			EmulpciREG(id,data)
#define pciREAD(id)				EmulpciREAD(id)
#define cpuREG(id,data)			EmulcpuREG(id,data)
#define cpuREAD(id)				EmulcpuREAD(id)
#define miuREG(id,data)			EmulmiuREG(id,data)
#define miuREAD(id)				EmulmiuREAD(id)
#else
#define EmulInit()
#define DumpReg()
#define DumpPal()
#define DumpCursor()
#define gcREG(base,id,data)		(REG32(base,id)=data)
#define gcREAD(base,id)        	(REG32(base,id))
#define gc1REG(id,data)      	(REG32(GC_BASE,id)=data)
#define gc1READ(id)				(REG32(GC_BASE,id))
#define gc2REG(id,data)			(REG32(GC_BASE,id)=data)
#define gc2READ(id)        		(REG32(GC_BASE,id))
#define fpREG(id,data)			(REG32(FP_BASE,id)=data)
#define fpREAD(id)				(REG32(FP_BASE,id))
#define g1pREG(idx,data)		(REG32_PAL(C1_BASE,idx)=data)
#define g1pREAD(idx)			(REG32_PAL(C1_BASE,idx))
#define g2pREG(idx,data)		(REG32_PAL(C2_BASE,idx)=data)
#define g2pREAD(idx)			(REG32_PAL(C2_BASE,idx))
//#define palREG(mmio,idx,data)	(REG32X_PAL(mmio,idx)=data)
//#define palREAD(mmio,idx)   	(REG32X_PAL(mmio,idx))
#define palREG(idx,data)		(REG32_PAL(C1_BASE,idx)=data)
#define palREAD(idx)   			(REG32_PAL(C1_BASE,idx))
#define dcREG(id,data)			(REG32(DC_BASE,id)=data)
#define dcREAD(id)    			(REG32(DC_BASE,id))
#define pmuREG(id,data)			(REG32(PM_BASE,id)=data)
#define pmuREAD(id)    			(REG32(PM_BASE,id))
#define pciREG(id,data)			(REG32(PC_BASE,id)=data)
#define pciREAD(id)				(REG32(PC_BASE,id))
#define cpuREG(id,data)			(REG32(CC_BASE,id)=data)
#define cpuREAD(id)         	(REG32(CC_BASE,id))
#define miuREG(id,data)			(REG32(MM_BASE,id)=data)
#define miuREAD(id)         	(REG32(MM_BASE,id))
#define intREG(id,data)			(REG32(IN_BASE,id)=data)
#define intREAD(id)         	(REG32(IN_BASE,id))
#endif // _EMUL_MQINIT

////////////////////////////////////////////////////////////////////////////
// Interrupt Controller
//
#define INT_CONTROL_REG		(0x00 * uBUSW)	// Global interrupt control reg
#define INT_MASK_REG		(0x01 * uBUSW)	// Interrupt mask register
#define INT_STATUS_REG		(0x02 * uBUSW)	// Interrupt status register
#define INT_RAW_STATUS_REG	(0x03 * uBUSW)	// Interrupt pin raw status reg

// INT_CONTROL_REG - Global Interrupt Control Register
//
#define INT_ENABLE			0x00000001		// MQ200 interrupt to CPU enabled
#define INT_PORLARITY_HIGH	0x00000002		// Interrupt is active high
#define INT_GPIO1_0To1		0x00000004		// Interrupt as transition 0 to 1
#define INT_GPIO2_0To1		0x00000008		// Interrupt as transition 0 to 1
#define INT_GPIO3_0To1		0x00000010		// Interrupt as transition 0 to 1

// INT_MASK_REG -- Interrupt Mask Register
//
#define UM_GC1_VSE_R		0x00000001		// GC1 VSE - Rising edge
#define UM_GC1_VSE_F		0x00000002		// GC1 VSE - Falling edge
#define UM_GC1_VDE_R		0x00000004		// GC1 VDE - Rising edge
#define UM_GC1_VDE_F		0x00000008		// GC1 VDE - Falling edge
#define UM_GC2_VSE_R		0x00000010		// GC2 VSE - Rising edge
#define UM_GC2_VSE_F		0x00000020		// GC2 VSE - Falling edge
#define UM_GC2_VDE_R		0x00000040		// GC2 VDE - Rising edge
#define UM_GC2_VDE_F		0x00000080		// GC2 VDE - Falling edge
#define UM_CFIFO_HALF_EMPTY	0x00000100		// Command fifo half empty
#define UM_CFIFO_EMPTY		0x00000200		// Command fifo empty
#define UM_SFIFO_HALF_EMPTY	0x00000400		// Source fifo half empty
#define UM_SFIFO_EMPTY		0x00000800		// Source fifo empty
#define UM_GE_IDLE			0x00001000		// GE is idle
#define UM_GPIO_1			0x00002000		// GPIO pin 1
#define UM_GPIO_2			0x00004000		// GPIO pin 2
#define UM_GPIO_3			0x00008000		// GPIO pin 3

// INT_STATUS_REG -- Interrupt Status Register
//
#define ST_GC1_VSE_R		0x00000001		// GC1 VSE - Rising edge
#define ST_GC1_VSE_F		0x00000002		// GC1 VSE - Falling edge
#define ST_GC1_VDE_R		0x00000004		// GC1 VDE - Rising edge
#define ST_GC1_VDE_F		0x00000008		// GC1 VDE - Falling edge
#define ST_GC2_VSE_R		0x00000010		// GC2 VSE - Rising edge
#define ST_GC2_VSE_F		0x00000020		// GC2 VSE - Falling edge
#define ST_GC2_VDE_R		0x00000040		// GC2 VDE - Rising edge
#define ST_GC2_VDE_F		0x00000080		// GC2 VDE - Falling edge
#define ST_CFIFO_HALF_EMPTY	0x00000100		// Command fifo half empty
#define ST_CFIFO_EMPTY		0x00000200		// Command fifo empty
#define ST_SFIFO_HALF_EMPTY	0x00000400		// Source fifo half empty
#define ST_SFIFO_EMPTY		0x00000800		// Source fifo empty
#define ST_GE_IDLE			0x00001000		// GE is idle
#define ST_GPIO_1			0x00002000		// GPIO pin 1
#define ST_GPIO_2			0x00004000		// GPIO pin 2
#define ST_GPIO_3			0x00008000		// GPIO pin 3

// INT_RAW_STATUA_REG -- Interrupt Pin Raw Status Register
//
#define GC1_VSE				0x00000001		// GC1 - VSE
#define GC1_VDE				0x00000004		// GC1 - VDE
#define GC2_VSE				0x00000010		// GC2 - VSE
#define GC2_VDE				0x00000040		// GC2 - VDE
#define INT_GE_BUSY			0x00000100		// GE busy
#define SFIFO_EMPTY			0x00000200		// Source fifo empty
#define SFIFO_HEMPTY		0x00000400		// Source fifo half empty
#define CFIFO_EMPTY			0x00000800		// Command fifo empty
#define CFIFO_HEMPTY		0x00001000		// Command fifo half empty
#define GPIO_PIN_1			0x00002000		// GPIO pin 1
#define GPIO_PIN_2			0x00004000		// GPIO pin 2
#define GPIO_PIN_3			0x00008000		// GPIO pin 3

// 2D Engine registers - GE1 (0x00 - 0x7F)
//
#define DRAW_CMD			(0x00 * uBUSW)	// Drawing command register
#define WIDTH_HEIGHT		(0x01 * uBUSW)	// Width/height register
#define	LINE_DRAW			WIDTH_HEIGHT	// Bresenham Line Draw register
#define DEST_XY				(0x02 * uBUSW)  // Destination X/Y register
#define LINE_MAJOR_X		DEST_XY         // Bresenham Line Start X/Y register
#define PAT_OFFSET			DEST_XY         // Pattern Offset register
#define SRC_XY				(0x03 * uBUSW)  // Source X/Y register
#define LINE_MINOR_Y		SRC_XY          // Bresenham Line Delta register
#define COLOR_COMPARE		(0x04 * uBUSW)  // Color compare register
#define CLIP_LeftT			(0x05 * uBUSW)  // Clip Left/Top register
#define CLIP_RightB			(0x06 * uBUSW)  // Clip Right/Bottom register
#define FG_COLOR			(0x07 * uBUSW)  // Foreground color for Mono src reg
#define BG_COLOR			(0x08 * uBUSW)  // Background color for Mono src reg
#define SRC_STRIDE_OFFSET	(0x09 * uBUSW)  // Source Stride & Offset Register
#define DEST_STRIDE			(0x0a * uBUSW)  // Base address register
#define BASE_ADDRESS		(0x0b * uBUSW)  // Base address register
#define TEST_RESULT_REG		(0x1f * uBUSW)  // Test result register
#define COLOR_PATTERN		(0x40 * uBUSW)  // Color pattern registers
#define MONO_PATTERN0		COLOR_PATTERN   // Mono Pattern register 0
#define MONO_PATTERN1		(0x41 * uBUSW)  // Mono Pattern register 1
#define PAT_FG_COLOR		(0x42 * uBUSW)  // Mono Pattern Foreground color reg
#define PAT_BG_COLOR		(0x43 * uBUSW)  // Mono Pattern Background color reg
#define	_FIRST_GE			DRAW_CMD
#define	_LAST_GE			(COLOR_PATTERN + (0x20 * uBUSW))

// 2D Engine registers - GE2 (0x80 to 0xFF)
//
#define DRAW_CMD2			(0x80 * uBUSW)  // Drawing command register
#define WIDTH_HEIGHT2		(0x81 * uBUSW)  // Width/height register
#define	LINE_DRAW2			WIDTH_HEIGHT2   // Bresenham Line Draw register
#define DEST_XY2			(0x82 * uBUSW)  // Destination X/Y register
#define LINE_MAJOR_X2		DEST_XY2		// Bresenham Line Start X/Y register
#define PAT_OFFSET2			DEST_XY2        // Pattern Offset register
#define SRC_XY2				(0x83 * uBUSW)  // Source X/Y register
#define LINE_MINOR_Y2		SRC_XY2			// Bresenham Line Delta register
#define COLOR_COMPARE2		(0x84 * uBUSW)  // Color compare register
#define CLIP_LeftT2			(0x85 * uBUSW)  // Clip Left/Top register
#define CLIP_RightB2		(0x86 * uBUSW)  // Clip Right/Bottom register
#define FG_COLOR2			(0x87 * uBUSW)  // Foreground color for Mono src reg
#define BG_COLOR2			(0x88 * uBUSW)  // Background color for Mono src reg
#define SRC_STRIDE_OFFSET2	(0x89 * uBUSW)  // Source Stride & Offset Register
#define DEST_STRIDE2		(0x8a * uBUSW)  // Base address register
#define BASE_ADDRESS2		(0x8b * uBUSW)  // Base address register
#define TEST_RESULT_REG2	(0x1f * uBUSW)	// Test result register
//#define SRC_IMAGE_DATA2		(0xa0 * uBUSW)	// Source Data register
#define SRC_IMAGE_DATA2		(0x3000 * uBUSW)	// Source Data register
#define COLOR_PATTERN2		(0xc0 * uBUSW)	// Color pattern registers
#define MONO_PATTERN02		COLOR_PATTERN2	// Mono Pattern register 0
#define MONO_PATTERN12		(0xc1 * uBUSW)	// Mono Pattern register 1
#define PAT_FG_COLOR2		(0xc2 * uBUSW)	// Mono Pattern Foreground color reg
#define PAT_BG_COLOR2		(0xc3 * uBUSW)  // Mono Pattern Background color reg
#define	_FIRST_GE2			DRAW_CMD2
#define	_LAST_GE2			(COLOR_PATTERN2 + (0x20 * uBUSW))


// DEST_STRIDE color depth
// 
#define GE_8BPP				0x00000000  	// 8BPP mode
#define GE_16BPP			0x40000000  	// 16BPP mode
#define GE_24BPP			0x80000000  	// 24BPP mode
#define GE_32BPP			0xC0000000  	// 24BPP mode

// BASE_ADDRESS
//
#define	GE_TEST_MODE_ENABLE	0x20000000		// Test mode enabled
#define GE_TEST_MASK		0xc0000000		// Test mode read path select
#define SEL_CLIP_LR			0x40000000		// Select clipping left/right
#define SEL_CLIP_TB			0x80000000		// Select clipping top/bottom

// Draw command register bits 
//
#define DO_BITBLT			0x00000200
#define	DO_AAFONT			0x00000300
#define	DO_LINEDRAW			0x00000400
#define X_DIR				0x00000800		// Negative X direction
#define Y_DIR				0x00001000		// Negative Y direction   
#define SRC_IS_MEMORY		0x00002000		// Source is in system memory
#define MONO_SRC			0x00004000		// Source is mono bitmap
#define MONO_PATTERN		0x00008000		// Pattern is monochrome
#define TRANS_COLOR			0x00010000		// Transparency is enabled
#define TRANS_NOT_EQUAL		0x00020000		// Polarity for color
#define TRANS_MONO			0x00040000		// Mono Transparency is enabled
#define TRANS_MONO_FG		0x00080000		// Polarity for mono
#define	PACKED_MODE			0x00100000		// Memory xfer mode select
#define	ALPHA_BYTE_MASK		0x00600000		// Alpha Byte mask for 32bpp
#define MONO_SOLID			0x00800000		// Solid Mono Pattern
#define SRC_NE_DEST_STRIDE	0x01000000		// Src Not Equal Dest Stride
#define	ROP2_ENABLE			0x02000000		// Use Rop2 code
#define CLIP_ENABLE			0x04000000		// Clipping is enabled
#define AUTO_EXEC			0x08000000		// Auto execute at dest X/Y
#define VDE_GC2_ENABLE		0x10000000		// Enable falling edge check
#define VDE_GC1_ENABLE		0x20000000		// Enable falling edge check
#define	COLOR_DEPTH_MASK	0xC0000000		// Color Depth mask
#define GE_8BPP				0x00000000		// 8BPP mode
#define GE_16BPP			0x40000000		// 16BPP mode
#define GE_24BPP			0x80000000		// 24BPP mode

#ifdef _USE_MQEMUL
#define	geSID( data )			EmulGeReg( SRC_IMAGE_DATA, data )
#define	geSRCFIFO( id, data )	EmulGeReg( SRC_IMAGE_DATA, data )
#else
#define	geSID( data )			(REG32(GE_BASE,SRC_IMAGE_DATA) = data)
#define	geSRCFIFO(id, data)		(REG32(S1_BASE,id) = data)
#endif	//_USE_MQEMUL

/////////////////////////////////////////////////////////////////////////////
// Graphics Controller 1 Registers
//
#define GC1_CONTROL			(0x00 * uBUSW)	// Graphics Controll 1 Control Reg
#define GC1_CRT_CONTROL		(0x01 * uBUSW)  // CRT controll register
#define HD1_CONTROL			(0x02 * uBUSW)  // Horizontal Display 1 Control
#define VD1_CONTROL			(0x03 * uBUSW)  // Vertical Display 1 Control
#define HS1_CONTROL			(0x04 * uBUSW)  // Horizontal Sync 1 Control
#define VS1_CONTROL			(0x05 * uBUSW)  // Vertical Sync 1 Control

#define HW1_CONTROL			(0x08 * uBUSW)  // Horizontal Window 1 Control
#define VW1_CONTROL			(0x09 * uBUSW)  // Vertical Window 1 Control
#define AHW1_CONTROL		(0x0a * uBUSW)  // Alt Horizontal Window 1 Control
#define AVW1_CONTROL		(0x0b * uBUSW)  // Alt Vertical Window 1 Control
#define IW1_START_ADDR		(0x0c * uBUSW)  // Image Window 1 Start Address
#define AIW1_START_ADDR		(0x0d * uBUSW)  // Alt Image Window 1 Start Address
#define IW1_STRIDE			(0x0e * uBUSW)  // (Alt) Image Window 1 Stride
#define IW1_LINE_SIZE		(0x0f * uBUSW)  // (Alt) Image Window 1 Line Size

// Hardware Cursor Registers
//
#define HW_CURSOR1_POS		(0x10 * uBUSW)  // Hardware cursor 1 position
#define HW_CURSOR1_ADDR		(0x11 * uBUSW)  // Start address and offset
#define HW_CURSOR1_FGCLR	(0x12 * uBUSW)  // Foreground color
#define HW_CURSOR1_BGCLR	(0x13 * uBUSW)  // Background color

// GC1_CONTROL/GC2_CONTROL register
//
#define GC_ENABLE			0x00000001UL	// Controll 1/2 enabled
#define GC_DISABLE     		0xfffffffeUL	// Controll 1/2 disabled
#define HORZ_COUNT_RESET  	0x00000002UL	// Horizontal counter 1/2 reset
#define VERT_COUNT_RESET  	0x00000004UL	// Vertical counter 1/2 reset
#define IM_ENABLE         	0x00000008UL	// Image Window 1/2 Enable
#define IM_DISABLE        	0xfffffff7UL	// Image Window 1/2 Disable
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mqhw2.h - 源码说明

本页面展示了「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等」中的 mqhw2.h 源码文件，采用 C头文件 编程语言编写，共 1,060 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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