kxmips.h
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H
795 行
/*++
Copyright (c) 1995, 1996, 1997 Microsoft Corporation
Module Name:
kxlcmips.h
Abstract:
This module contains the nongenerated part of the MIPS assembler
Theader file. In general, it contains processor architecture constant
information, however some assembler macros are also included.
Author:
David N. Cutler (davec) 23-Mar-1990
Revision History:
Jun Liu 12-Jul-1996 - Add support for MIPS R4300i processor
John Cooper (johncoop) 97-Oct-20: Port to LC2W platform
Note:
To choose which CPU to use, define following macro as appropriate:
R3000 for MIPS R3000 processor
R4000 for MIPS R4000 processor
R4300 for MIPS R4300 processor
--*/
/*
** Define load linked and store conditional opcodes if system is an r3000
*/
#if defined(R3000)
#define ll lw
#define sc sw
#endif
/*
** Define soft reset vector address for nonhandled cache parity errors.
*/
#if defined(R4000) || defined(R4300) || defined(R5230)
#define SOFT_RESET_VECTOR 0xbfc00300 /* default parity error routine address */
#endif
/*
** Define low memory transfer vector address and TB index address (temporary).
*/
#define TRANSFER_VECTOR (KSEG1_BASE + 0x400) /* exception handler address */
#ifndef REGISTER_DEFINED
/*
** Define standard integer registers.
*/
#define zero $0 /* read zero, writes ignored */
#define AT $1 /* assembler temporary */
#define v0 $2 /* return value */
#define v1 $3 /* */
#define a0 $4 /* argument registers */
#define a1 $5 /* */
#define a2 $6 /* */
#define a3 $7 /* */
#define t0 $8 /* caller saved registers */
#define t1 $9 /* */
#define t2 $10 /* */
#define t3 $11 /* */
#define t4 $12 /* */
#define t5 $13 /* */
#define t6 $14 /* */
#define t7 $15 /* */
#define s0 $16 /* callee saved registers */
#define s1 $17 /* */
#define s2 $18 /* */
#define s3 $19 /* */
#define s4 $20 /* */
#define s5 $21 /* */
#define s6 $22 /* */
#define s7 $23 /* */
#define t8 $24 /* caller saved registers */
#define t9 $25 /* */
#define k0 $26 /* kernel reserved registers */
#define k1 $27 /* */
#define gp $28 /* global pointer */
#define sp $29 /* stack pointer */
#define s8 $30 /* callee saved register */
#define ra $31 /* return address register */
/*
** Define standard floating point registers.
*/
#define f0 $f0 /* caller saved registers */
#define f1 $f1 /* */
#define f2 $f2 /* */
#define f3 $f3 /* */
#define f4 $f4 /* */
#define f5 $f5 /* */
#define f6 $f6 /* */
#define f7 $f7 /* */
#define f8 $f8 /* */
#define f9 $f9 /* */
#define f10 $f10 /* */
#define f11 $f11 /* */
#define f12 $f12 /* */
#define f13 $f13 /* */
#define f14 $f14 /* */
#define f15 $f15 /* */
#define f16 $f16 /* */
#define f17 $f17 /* */
#define f18 $f18 /* */
#define f19 $f19 /* */
#define f20 $f20 /* callee saved registers */
#define f21 $f21 /* */
#define f22 $f22 /* */
#define f23 $f23 /* */
#define f24 $f24 /* */
#define f25 $f25 /* */
#define f26 $f26 /* */
#define f27 $f27 /* */
#define f28 $f28 /* */
#define f29 $f29 /* */
#define f30 $f30 /* */
#define f31 $f31 /* */
#endif /* End of REGISTER_DEFINED */
/*
** Define R3000 system coprocessor registers.
*/
#if defined(R3000)
#ifndef REGISTER_DEFINED
#define index $0 /* TB index register */
#define random $1 /* TB random register */
#define entrylo $2 /* TB entry low register */
#define context $4 /* TB context register */
#define badvaddr $8 /* TB bad virtual address register */
#define entryhi $10 /* TB entry high register */
#define psr $12 /* processor status register */
#define cause $13 /* exception cause register */
#define epc $14 /* exception PC register */
#define prid $15 /* processor id register */
#endif /* End of REGISTER_DEFINED */
/*
** Define R3000 system coprocessor register bit field offsets.
*/
#define INDEX_INDEX 0x8 /* TLB specified index <13:8> */
#define INDEX_PROBE 0x1f /* TLB probe failure <31> */
#define RANDOM_INDEX 0x8 /* TLB random index <13:8> */
#define ENTRYLO_G 0x8 /* Global <8> */
#define ENTRYLO_V 0x9 /* Valid <9> */
#define ENTRYLO_D 0xa /* Dirty <10> */
#define ENTRYLO_N 0xb /* Nocache <11> */
#define ENTRYLO_PFN 0xc /* Page Frame <31: 12> */
#define ENTRYHI_PID 0x6 /* Process id <11:6> */
#define ENTRYHI_VPN 0xc /* Virtual page <31:12> */
#define PSR_IEC 0x0 /* Current interrupt enable <0> */
#define PSR_KUC 0x1 /* Current kernel/user <1> */
#define PSR_IEP 0x2 /* Previous interrupt enable <2> */
#define PSR_KUP 0x3 /* Previous kernel/user <3> */
#define PSR_PMODE PSR_KUP /* Previous mode bit <3> */
#define PSR_IEO 0x4 /* Old interrupt enable <4> */
#define PSR_KUO 0x5 /* Old kernel/user <5> */
#define PSR_INTMASK 0x8 /* Interrupt mask <15:8> */
#define PSR_ISC 0x10 /* Isolate d-cache <16> */
#define PSR_SWC 0x11 /* Swap caches <17> */
#define PSR_PZ 0x12 /* Parity zero <18> */
#define PSR_CM 0x13 /* Cache miss <19> */
#define PSR_PE 0x14 /* Parity error <20> */
#define PSR_TS 0x15 /* TLB shutdown <21> */
#define PSR_BEV 0x16 /* Bootstrap exception vector <22> */
#define PSR_CU0 0x1c /* Coprocessor 0 enabled <28> */
#define PSR_CU1 0x1d /* Coprocessor 1 enabled <29> */
#define PSR_CU2 0x1e /* Coprocessor 2 enabled <30> */
#define PSR_CU3 0x1f /* Coprocessor 3 enabled <31> */
#endif
/*
** Define R4000 & R4300 system coprocessor registers.
*/
#if defined(R4000) || defined(R4300) || defined(R5230)
#ifndef REGISTER_DEFINED
#define index $0 /* TB index register */
#define random $1 /* TB random register */
#define entrylo0 $2 /* TB entry low 0 register */
#define entrylo1 $3 /* TB entry low 1 register */
#define context $4 /* TB context register */
#define pagemask $5 /* Page mask register */
#define wired $6 /* Wired TB entries register */
#define badvaddr $8 /* TB bad virtual address register */
#define count $9 /* Timer count register */
#define entryhi $10 /* TB entry high register */
#define compare $11 /* Timer compare register */
#define psr $12 /* Processor status register */
#define cause $13 /* Exception cause register */
#define epc $14 /* Exception PC register */
#define prid $15 /* Processor id register */
#define config $16 /* Configuration register */
#define lladdr $17 /* Load linked address register */
#define watchlo $18 /* Watch low address register */
#define watchhi $19 /* Watch high address register */
#define ecc $26 /* S-cache ECC and primary parity register */
#define cacheerr $27 /* Cache error and status register */
#define taglo $28 /* Cache tag low register */
#define taghi $29 /* Cache tag high register */
#define errorepc $30 /* Error exception PC register */
#endif /* End of REGISTER_DEFINED */
/*
** Define R4000 and R4300 system coprocessor register bit field offsets.
*/
#define INDEX_INDEX 0x0 /* TLB specified index <5:0> */
#define INDEX_PROBE 0x1f /* TLB probe failure <31> */
#define RANDOM_INDEX 0x0 /* TLB random index <5:0> */
#define ENTRYLO_G 0x0 /* Global <0> */
#define ENTRYLO_V 0x1 /* Valid <1> */
#define ENTRYLO_D 0x2 /* Dirty <2> */
#define ENTRYLO_C 0x3 /* Cache control <5:3> */
#define ENTRYLO_PFN 0x6 /* Page Frame <29:6> */
#define PAGEMASK_PAGEMASK 0xd /* Page mask <24:13> */
#define WIRED_NUMBER 0x0 /* Wired entries <5:0> */
#define ENTRYHI_PID 0x0 /* Process id <7:0> */
#define ENTRYHI_VPN2 0xd /* Virtual page <31:13 > */
#define PID_MASK 0xfff /* allow for ample expansion */
#define PSR_IE 0x0 /* Interrupt enable <0> */
#define PSR_EXL 0x1 /* Exception level <1> */
#define PSR_ERL 0x2 /* Error level <2> */
#define PSR_KSU 0x3 /* Kernel/supervisor/user <4:3> */
#define PSR_PMODE (PSR_KSU + 1) /* Previous mode bit <4> */
#define PSR_UX 0x5 /* User extended <5> */
#define PSR_SX 0x6 /* Supervior extended <6> */
#define PSR_KX 0x7 /* Kernel extended <7> */
#define PSR_INTMASK 0x8 /* Interrupt mask <15:8> */
#define PSR_DE 0x10 /* Disable cache parity and ECC <16> */
#define PSR_CE 0x11 /* Check enable <17> */
#define PSR_CH 0x12 /* Cache hit <18> */
#define PSR_SR 0x14 /* Soft reset <20> */
#define PSR_TS 0x15 /* TLB shutdown <21> */
#define PSR_BEV 0x16 /* Bootstrap exception vector <22> */
#define PSR_FR 0x1a /* Enable additional FP register */
#define PSR_CU0 0x1c /* Coprocessor 0 enabled <28> */
#define PSR_CU1 0x1d /* Coprocessor 1 enabled <29> */
#define PSR_CU2 0x1e /* Coprocessor 2 enabled <30> */
#define PSR_CU3 0x1f /* Coprocessor 3 enabled <31> */
#define CONFIG_K0 0x0 /* Kseg0 cache algorithm <2:0> */
#define CONFIG_CU 0x3 /* Update on store conditional <3> */
#define CONFIG_DB 0x4 /* Data cache block size <4> */
#define CONFIG_IB 0x5 /* Instruction cache block size <5> */
#define CONFIG_DC 0x6 /* Data cache size <8:6> */
#define CONFIG_IC 0x9 /* Instruction cache size <11:9> */
#define CONFIG_EB 0xd /* Block ordering <13> */
#define CONFIG_EM 0xe /* ECC mode enable <14> */
#define CONFIG_BE 0xf /* Big endian memory <15> */
#define CONFIG_SM 0x10 /* Use dirty shared state <16> */
#define CONFIG_SC 0x11 /* Secondary cache present <17> */
#define CONFIG_EW 0x12 /* System address port width <19:18> */
#define CONFIG_SW 0x14 /* Secondary cache port width <20> */
#define CONFIG_SS 0x15 /* Split secondary cache mode <21> */
#define CONFIG_SB 0x16 /* Secondary cache block size <23:22> */
#define CONFIG_EP 0x18 /* Pattern for write back data <27:24> */
#define CONFIG_EC 0x1c /* System address port clock ratio <30:28> */
#define CONFIG_CM 0x1f /* Master checker mode <31> */
#define ECC_ECC 0x0 /* Secondary cache ECC <7:0> */
#define CACHEERR_PIDX 0x0 /* Primary cache index <2:0> */
#define CACHEERR_SIDX 0x3 /* Secondary cache index <21:3> */
#define CACHEERR_EI 0x18 /* ECC error on pimary store miss <24> */
#define CACHEERR_EB 0x19 /* Data error on instrruction error <25> */
#define CACHEERR_EE 0x1a /* Error on system address bus <26> */
#define CACHEERR_ES 0x1b /* Error accessing processor state <27 > */
#define CACHEERR_ET 0x1c /* Error on tag field <28> */
#define CACHEERR_ED 0x1d /* Error on data field <29> */
#define CACHEERR_EC 0x1e /* Cache level of error <30> */
#define CACHEERR_ER 0x1f /* Type of reference <31> */
#define TAGLO_P 0x0 /* primary tag even parity <0> */
#define TAGLO_PSTATE 0x6 /* primary cache state <7:6> */
#define TAGLO_PTAGLO 0x8 /* primary tag low physical address <31:8> */
#endif
/*
** Define R3000 and R4000 cause register bit offsets.
*/
#define CAUSE_XCODE 0x2 /* Exception code <6:2> */
#define CAUSE_INTPEND 0x8 /* Interrupt pending <15:8> */
#define CAUSE_IV 0x17 /* Interrupt vector enable <23> */
#define CAUSE_CE 0x1c /* Coprocessor unusable <29:28) */
#define CAUSE_BD 0x1f /* Branch delay slot <31> */
/*
** Define R3000 and R4000 processor id register field offsets.
*/
#define PRID_REV 0x0 /* Revision level <7:0> */
#define PRID_IMP 0x8 /* Implementation type <15:8> */
/*
** Define R3000 and R4000 exception codes.
*/
#define XCODE_INTERRUPT 0x0 /* Interrupt */
#define XCODE_MODIFY 0x4 /* TLB modify */
#define XCODE_READ_MISS 0x8 /* TLB read miss */
#define XCODE_WRITE_MISS 0xc /* TLB write miss */
#define XCODE_READ_ADDRESS_ERROR 0x10 /* Read alignment error */
#define XCODE_WRITE_ADDRESS_ERROR 0x14 /* Write alignment error */
#define XCODE_INSTRUCTION_BUS_ERROR 0x18 /* Instruction bus error */
#define XCODE_DATA_BUS_ERROR 0x1c /* Data bus error */
#define XCODE_SYSTEM_CALL 0x20 /* System call */
#define XCODE_BREAKPOINT 0x24 /* Breakpoint */
#define XCODE_ILLEGAL_INSTRUCTION 0x28 /* Illegal instruction */
#define XCODE_COPROCESSOR_UNUSABLE 0x2c /* Coprocessor unusable */
#define XCODE_INTEGER_OVERFLOW 0x30 /* Arithmetic overflow */
#if defined(R3000)
#define XCODE_PANIC 0x3c /* Stack overflow (software) */
#define R3000_XCODE_MASK (0xf << CAUSE_XCODE) /* R3000 exception code mask */
#define R3000_MISS_MASK (R3000_XCODE_MASK & \
(~(XCODE_READ_MISS ^ XCODE_WRITE_MISS))) /* */
#endif
#if defined(R4000) || defined(R5230)
#define XCODE_TRAP 0x34 /* Trap instruction */
#define XCODE_VIRTUAL_INSTRUCTION 0x38 /* Virtual instruction coherency */
#define XCODE_FLOATING_EXCEPTION 0x3c /* Floating point exception */
#define XCODE_WATCHPOINT 0x5c /* Watch point */
#define XCODE_PANIC 0x78 /* Stack overflow (software) */
#define XCODE_VIRTUAL_DATA 0x7c /* Virtual data coherency */
#define R4000_XCODE_MASK (0x1f << CAUSE_XCODE) /* R4000 exception code mask */
#define R4000_MISS_MASK (R4000_XCODE_MASK & \
(~(XCODE_READ_MISS ^ XCODE_WRITE_MISS))) /* */
#endif
/*
** Define R4000 page mask values.
*/
#if defined(R4000) || defined(R5230)
#define PAGEMASK_4KB 0x0 /* 4kb page */
#define PAGEMASK_16KB 0x3 /* 16kb page */
#define PAGEMASK_64KB 0xf /* 64kb page */
#define PAGEMASK_256KB 0x3f /* 256kb page */
#define PAGEMASK_1MB 0xff /* 1mb page */
#define PAGEMASK_4MB 0x3ff /* 4mb page */
#define PAGEMASK_16MB 0xfff /* 16mb page */
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