kxmips.h
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 795 行 · 第 1/2 页
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#endif
/*
** Define R4000 primary cache states.
*/
#if defined(R4000) || defined(R5230)
#define PRIMARY_CACHE_INVALID 0x0 /* primary cache invalid */
#define PRIMARY_CACHE_SHARED 0x1 /* primary cache shared (clean or dirty) */
#define PRIMARY_CACHE_CLEAN_EXCLUSIVE 0x2 /* primary cache clean exclusive */
#define PRIMARY_CACHE_DIRTY_EXCLUSIVE 0x3 /* primary cache dirty exclusive */
#endif
/*
** Define R4000 cache instruction operation codes.
*/
#if defined(R4000) | defined(R4300) | defined(R5230)
#define INDEX_INVALIDATE_I 0x0 /* invalidate primary instruction cache */
#define INDEX_WRITEBACK_INVALIDATE_D 0x1 /* writeback/invalidate primary data cache */
#define INDEX_INVALIDATE_SI 0x2 /* invalidate secondary instruction cache */
#define INDEX_WRITEBACK_INVALIDATE_SD 0x3 /* writeback/invalidate secondary data cache */
#define INDEX_LOAD_TAG_I 0x4 /* load primary instruction tag indexed */
#define INDEX_LOAD_TAG_D 0x5 /* load primary data tag indexed */
#define INDEX_LOAD_TAG_SI 0x6 /* load secondary instruction tag indexed */
#define INDEX_LOAD_TAG_SD 0x7 /* load secondary data tag indexed */
#define INDEX_STORE_TAG_I 0x8 /* store primary instruction tag indexed */
#define INDEX_STORE_TAG_D 0x9 /* store primary data tag indexed */
#define INDEX_STORE_TAG_SI 0xa /* store secondary instruction tag indexed */
#define INDEX_STORE_TAG_SD 0xb /* store secondary data tag indexed */
#define CREATE_DIRTY_EXCLUSIVE_D 0xd /* create dirty exclusive primary data cache */
#define CREATE_DIRTY_EXCLUSIVE_SD 0xf /* create dirty exclusive secondary data cache */
#define HIT_INVALIDATE_I 0x10 /* invalidate primary instruction cache */
#define HIT_INVALIDATE_D 0x11 /* invalidate primary data cache */
#define HIT_INVALIDATE_SI 0x12 /* invalidate secondary instruction cache */
#define HIT_INVALIDATE_SD 0x13 /* invalidate secondary data cache */
#define INDEX_FILL_I 0x14
#define HIT_WRITEBACK_INVALIDATE_D 0x15 /* writeback/invalidate primary data cache */
#define HIT_WRITEBACK_INVALIDATE_SD 0x17 /* writeback/invalidate secondary data cache */
#define HIT_WRITEBACK_I 0x18
#define HIT_WRITEBACK_D 0x19 /* writeback primary data cache */
#define HIT_WRITEBACK_SD 0x1b /* writeback secondary data cache */
#define HIT_SET_VIRTUAL_SI 0x1e /* hit set virtual secondary instruction cache */
#define HIT_SET_VIRTUAL_SD 0x1f /* hit set virtual secondary data cache */
#define SECONDARY_CACHE_SIZE (1 << 20)
#define SECONDARY_CACHE_INVALID 0x0
#define TAGLO_SSTATE 0xA
#endif
/*
** Define enable and disable interrupt macros.
*/
#if defined(R3000)
#define DISABLE_INTERRUPTS(reg) \
.set noreorder; \
.set noat; \
li AT,1 << PSR_CU1; \
mfc0 reg,psr; \
mtc0 AT,psr; \
nop; \
nop; \
.set at; \
.set reorder;
#define ENABLE_INTERRUPTS(reg) \
.set noreorder; \
.set noat; \
mtc0 reg,psr; \
nop; \
.set at; \
.set reorder;
#endif
#if defined(R4000)
#define DISABLE_INTERRUPTS(reg) \
.set noreorder; \
.set noat; \
li AT,1 << PSR_CU1; \
mfc0 reg,psr; \
mtc0 AT,psr; \
nop; \
nop; \
nop; \
.set at; \
.set reorder;
#define ENABLE_INTERRUPTS(reg) \
.set noreorder; \
.set noat; \
mtc0 reg,psr; \
nop; \
nop; \
.set at; \
.set reorder;
#endif
/*
** Define floating coprocessor registers
*/
#define fsrid $0 /* floating identification register */
#define fsr $31 /* floating status register */
/*
** Define floating status register bit offsets.
*/
#define FSR_RM 0x0
#define FSR_SI 0x2
#define FSR_SU 0x3
#define FSR_SO 0x4
#define FSR_SZ 0x5
#define FSR_SV 0x6
#define FSR_EI 0x7
#define FSR_EU 0x8
#define FSR_EO 0x9
#define FSR_EZ 0xa
#define FSR_EV 0xb
#define FSR_XI 0xc
#define FSR_XU 0xd
#define FSR_XO 0xe
#define FSR_XZ 0xf
#define FSR_XV 0x10
#define FSR_XE 0x11
#define FSR_CC 0x17
#define FSR_FS 0x18
/*
** Define save and restore floating state macros.
*/
#if defined(R3000)
#define RESTORE_VOLATILE_FLOAT_STATE \
.set noreorder; \
jal KiRestoreVolatileFloatState; \
lwc1 f0,TrFltF0(s8); \
.set reorder;
#define SAVE_VOLATILE_FLOAT_STATE \
.set noreorder; \
jal KiSaveVolatileFloatState; \
swc1 f0,TrFltF0(s8); \
.set reorder;
#endif
#if defined(R4000)
#define RESTORE_VOLATILE_FLOAT_STATE \
.set noreorder; \
jal KiRestoreVolatileFloatState; \
ldc1 f0,TrFltF0(s8); \
.set reorder;
#define SAVE_VOLATILE_FLOAT_STATE \
.set noreorder; \
jal KiSaveVolatileFloatState; \
sdc1 f0,TrFltF0(s8); \
.set reorder;
#endif
#if defined(R3000)
#define RESTORE_NONVOLATILE_FLOAT_STATE \
.set noreorder; \
jal KiRestoreNonvolatileFloatState; \
lwc1 f20,ExFltF20(sp); \
.set reorder;
#define SAVE_NONVOLATILE_FLOAT_STATE \
.set noreorder; \
jal KiSaveNonvolatileFloatState; \
swc1 f20,ExFltF20(sp); \
.set reorder;
#endif
#if defined(R4000)
#define RESTORE_NONVOLATILE_FLOAT_STATE \
.set noreorder; \
jal KiRestoreNonvolatileFloatState; \
ldc1 f20,ExFltF20(sp); \
.set reorder;
#define SAVE_NONVOLATILE_FLOAT_STATE \
.set noreorder; \
jal KiSaveNonvolatileFloatState; \
sdc1 f20,ExFltF20(sp); \
.set reorder;
#endif
/*
** Define TB and cache parameters.
*/
#if defined(R3000)
#define NUMBER_PIDS 64 /* number of process ids */
#define PCR_ENTRY 0 /* TB entry numbers (2) for the PCR */
#define PDR_ENTRY 2 /* TB entry number (1) for the PDR */
#define KSTACK_ENTRY 3 /* TB entry numbers (2) for kernel stack */
#define KDPORT_ENTRY 5 /* TB entry number (1) for debug port */
#define DMA_ENTRY 6 /* TB entry number (1) for DMA registers */
#define INTERRUPT_ENTRY 7 /* TB entry number (1) for interrupt source */
#define TB_SIZE 64 /* number of TB entries */
#define TB_ENTRY_SIZE (2 * 4) /* size of TB entry */
#define FIXED_BASE 0 /* base index of fixed TB entries */
#define FIXED_ENTRIES (INTERRUPT_ENTRY + 1) /* number of fixed TB entries */
#define RANDOM_BASE FIXED_ENTRIES /* base index of random TB entries */
#define RANDOM_ENTRIES (TB_SIZE - RANDOM_BASE) /* number of random TB entries */
#endif
#if defined(R4000) && !defined(R4300)
#define PCR_ENTRY 0 /* TB entry numbers (2) for the PCR */
#define PDR_ENTRY 2 /* TB entry number (1) for the PDR */
#define LARGE_ENTRY 3 /* TB entry number (1) for large entry */
#define DMA_ENTRY 4 /* TB entry number (1) for DMA/InterruptSource */
#define TB_ENTRY_SIZE (3 * 4) /* size of TB entry */
#define FIXED_BASE 0 /* base index of fixed TB entries */
#define FIXED_ENTRIES (DMA_ENTRY + 1) /* number of fixed TB entries */
#endif
#if defined(R4300)
#define TB_ENTRY_SIZE (4 * 4) /* size of TB entry */
#define TB_SIZE 32 /* number of TB entries */
#endif
#if defined(R5230)
#define TB_ENTRY_SIZE (4 * 4) /* size of TB entry */
#define TB_SIZE 48 /* number of TB entries */
#endif
/*
** Define cache parameters
*/
#define DCACHE_SIZE 4 * 1024 /* size of data cache in bytes */
#define ICACHE_SIZE 4 * 1024 /* size of instruction cache in bytes */
#define MINIMUM_CACHE_SIZE 4 * 1024 /* minimum size of cache */
#define MAXIMUM_CACHE_SIZE 128 * 1024 /* maximum size fo cache */
/*
** Define subtitle macro
*/
#define SBTTL(x)
/*
** Define global definition macros.
*/
#define END_REGION(Name) \
.globl Name; \
Name:;
#define START_REGION(Name) \
.globl Name; \
Name:;
/*
** Define trap frame generation macro.
*/
#define GENERATE_TRAP_FRAME \
.set noreorder; \
.set noat; \
jal KiGenerateTrapFrame; \
sw AT,TrIntAt(s8); \
.set at; \
.set reorder;
/*
** Define restore volatile integer state macro.
*/
#define RESTORE_VOLATILE_INTEGER_STATE \
.set noreorder; \
.set noat; \
jal KiRestoreVolatileIntegerState; \
lw AT,TrIntAt(s8); \
.set at; \
.set reorder;
/*
** Define save volatile integer state macro.
*/
#define SAVE_VOLATILE_INTEGER_STATE \
.set noreorder; \
.set noat; \
jal KiSaveVolatileIntegerState; \
sw AT,TrIntAt(s8); \
.set at; \
.set reorder;
/*
** Define procedure entry macros
*/
#define ALTERNATE_ENTRY(Name) \
.globl Name; \
Name:;
#define LEAF_ENTRY(Name) \
.text; \
.globl Name; \
.ent Name, 0; \
Name:; \
.frame sp, 0, ra; \
.prologue 0;
#define NESTED_ENTRY(Name, fsize, retrg) \
.text; \
.globl Name; \
.ent Name, 0; \
Name:; \
.frame sp, fsize, retrg;
#define ALTERNATE_ENTRY_S(Name) \
.globl Name; \
Name:;
#define SYSTEM_ENTRY(Name) \
.text; \
.globl Name; \
.ent Name, 0; \
Name:; \
.frame sp, 0, ra; \
.prologue 0;
#define LEAF_ENTRY_S(Name, Section) \
.text Section; \
.globl Name; \
.ent Name, 0; \
Name:; \
.frame sp, 0, ra; \
.prologue 0;
#define NESTED_ENTRY_S(Name, fsize, retrg, Section) \
.text Section; \
.globl Name; \
.ent Name, 0; \
Name:; \
.frame sp, fsize, retrg;
/*
** Define exception handling macros.
*/
#define EXCEPTION_HANDLER(Handler) \
.edata 1, Handler;
#define PROLOGUE_END .prologue 1;
/*
** Define exception data section and align.
*/
#ifndef HEADER_FILE
.edata 0
.text
#endif
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