vector.s

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/*++
Copyright (c) 1997  Microsoft Corporation

Module Name:

        vector.s

Abstract:

        This module contains the exception handling vectors.

Author:

        Jun Liu 01-Aug-96

--*/

#include "kxmips.h"
#include "alt_def.h"
#include "romdef.h"


/////////////////////////////////////////////////////////////////
//
// The exception vector
//
// The vectors should be copied into the KSEG1(0) space in order
// to service exception correctly. Call InitializeExceptionVector
// to do the copy job.
//

LEAF_ENTRY(ExceptionVector)

    .set    noreorder
    .set    noat

//
// TLB refill exception vector
//
Vector_TLBRefill:

    sw      sp,(spRegTable-RegisterTableSize)(sp)
    subu    sp,sp,RegisterTableSize

    sw      t1,t1RegTable(sp)
    sw      t2,t2RegTable(sp)
    sw      t3,t3RegTable(sp)
    sw      t4,t4RegTable(sp)
    sw      t5,t5RegTable(sp)
    sw      t6,t6RegTable(sp)
    sw      t7,t7RegTable(sp)
    sw      t8,t8RegTable(sp)
    sw      t9,t9RegTable(sp)
    sw      a0,a0RegTable(sp)
    sw      a1,a1RegTable(sp)
    sw      a2,a2RegTable(sp)
    sw      a3,a3RegTable(sp)
    sw      t0,t0RegTable(sp)
    sw      AT,atRegTable(sp)
    sw      v0,v0RegTable(sp)
    sw      v1,v1RegTable(sp)
    sw      k0,k0RegTable(sp)
    sw      k1,k1RegTable(sp)
    sw      gp,gpRegTable(sp)
    sw      ra,raRegTable(sp)

    move    a0,sp                       // pass regTable base address

    jal     TLBExceptionHandler
    nop

    lw      ra,raRegTable(sp)
    lw      sp,spRegTable(sp)

    eret
    nop

End_TLBRefill:


//
// XTLB refill exception vector
//
Vector_XTLBRefill:

    sw      sp,(spRegTable-RegisterTableSize)(sp)
    subu    sp,sp,RegisterTableSize

    sw      t1,t1RegTable(sp)
    sw      t2,t2RegTable(sp)
    sw      t3,t3RegTable(sp)
    sw      t4,t4RegTable(sp)
    sw      t5,t5RegTable(sp)
    sw      t6,t6RegTable(sp)
    sw      t7,t7RegTable(sp)
    sw      t8,t8RegTable(sp)
    sw      t9,t9RegTable(sp)
    sw      a0,a0RegTable(sp)
    sw      a1,a1RegTable(sp)
    sw      a2,a2RegTable(sp)
    sw      a3,a3RegTable(sp)
    sw      t0,t0RegTable(sp)
    sw      AT,atRegTable(sp)
    sw      v0,v0RegTable(sp)
    sw      v1,v1RegTable(sp)
    sw      k0,k0RegTable(sp)
    sw      k1,k1RegTable(sp)
    sw      gp,gpRegTable(sp)
    sw      ra,raRegTable(sp)

    move    a0,sp                       // pass regTable base address
    jal     XTLBExceptionHandler

    lw      ra,raRegTable(sp)
    lw      sp,spRegTable(sp)

    nop
    eret
    nop

End_XTLBRefill:


//
// Cache Error exception vector
//
Vector_CacheError:

    sw      sp,(spRegTable-RegisterTableSize)(sp)
    subu    sp,sp,RegisterTableSize

    sw      t1,t1RegTable(sp)
    sw      t2,t2RegTable(sp)
    sw      t3,t3RegTable(sp)
    sw      t4,t4RegTable(sp)
    sw      t5,t5RegTable(sp)
    sw      t6,t6RegTable(sp)
    sw      t7,t7RegTable(sp)
    sw      t8,t8RegTable(sp)
    sw      t9,t9RegTable(sp)
    sw      a0,a0RegTable(sp)
    sw      a1,a1RegTable(sp)
    sw      a2,a2RegTable(sp)
    sw      a3,a3RegTable(sp)
    sw      t0,t0RegTable(sp)
    sw      AT,atRegTable(sp)
    sw      v0,v0RegTable(sp)
    sw      v1,v1RegTable(sp)
    sw      k0,k0RegTable(sp)
    sw      k1,k1RegTable(sp)
    sw      gp,gpRegTable(sp)
    sw      ra,raRegTable(sp)

    move    a0,sp                       // pass regTable base address
    jal     CacheErrorExceptionHandler

    lw      ra,raRegTable(sp)
    lw      sp,spRegTable(sp)

    nop
    eret
    nop

End_CacheError:

//
// Other exception vector
//
Vector_Other:

    sw      sp,(spRegTable-RegisterTableSize)(sp)
    subu    sp,sp,RegisterTableSize

    sw      t1,t1RegTable(sp)
    sw      t2,t2RegTable(sp)
    sw      t3,t3RegTable(sp)
    sw      t4,t4RegTable(sp)
    sw      t5,t5RegTable(sp)

    mfc0    t1,cause                    // get cause
    la      t2,OtherExceptionTable      // get jump table entry
    li      t3,0x0000007c               // get exec code bit mask

    sw      t6,t6RegTable(sp)
    sw      t7,t7RegTable(sp)
    sw      t8,t8RegTable(sp)
    sw      t9,t9RegTable(sp)

    and     t3,t3,t1                    // pick exec code

    sw      a0,a0RegTable(sp)
    sw      a1,a1RegTable(sp)
    sw      a2,a2RegTable(sp)
    sw      a3,a3RegTable(sp)

    sll     t3,t3,2                     // compute jump offset

    sw      t0,t0RegTable(sp)
    sw      AT,atRegTable(sp)
    sw      v0,v0RegTable(sp)
    sw      v1,v1RegTable(sp)

    move    a0,sp                       // pass regTable base address
    addu    t2,t3,t2                    // compute entry address

    sw      k0,k0RegTable(sp)
    sw      k1,k1RegTable(sp)
    sw      gp,gpRegTable(sp)
    sw      ra,raRegTable(sp)

    j       t2
    nop

End_Other:

    .end    ExceptionVector




/////////////////////////////////////////////////////////////////
//
// Initialize exception vector
//

LEAF_ENTRY(InitializeExceptionVector)

    .set    noreorder
    .set    noat

    la      t1,Vector_TLBRefill         // start of TLB refill vector
    la      t3,KSEG1_BASE+0x00          // system location of vector
    la      t2,End_TLBRefill            // end of TLB refill vector

LpCpTLB:
    lw      t4,0(t1)                    // load source data
    addu    t1,t1,4                     // increment source counter
    sw      t4,0(t3)                    // write target data
    bne     t1,t2,LpCpTLB               // loop until done
    addu    t3,t3,4                     // increment target counter


    la      t1,Vector_XTLBRefill        // start of XTLB refill vector
    la      t3,KSEG1_BASE+0x80          // system location of vector
    la      t2,End_XTLBRefill           // end of XTLB refill vector

LpCpXTLB:
    lw      t4,0(t1)                    // load source data
    addu    t1,t1,4                     // increment source counter
    sw      t4,0(t3)                    // write target data
    bne     t1,t2,LpCpXTLB              // loop until done
    addu    t3,t3,4                     // increment target counter


    la      t1,Vector_CacheError        // start of XTLB refill vector
    la      t3,KSEG1_BASE+0x100         // system location of vector
    la      t2,End_CacheError           // end of XTLB refill vector

LpCpCacheError:
    lw      t4,0(t1)                    // load source data
    addu    t1,t1,4                     // increment source counter
    sw      t4,0(t3)                    // write target data
    bne     t1,t2,LpCpCacheError        // loop until done
    addu    t3,t3,4                     // increment target counter

    la      t1,Vector_Other             // start of other vector
    la      t3,KSEG1_BASE+0x180         // system location of vector
    la      t2,End_Other                // end of other vector

LpCpOther:
    lw      t4,0(t1)                    // load source data
    addu    t1,t1,4                     // increment source counter
    sw      t4,0(t3)                    // write target data
    bne     t1,t2,LpCpOther             // loop until done
    addu    t3,t3,4                     // increment target counter


    j       ra
    nop

    .end    InitializeExceptionVector


/////////////////////////////////////////////////////////////////
//
// Other exception jump table
//


#define OTHER_EXCEPTION_ENTRY(name)             \
    jal     name;                               \
    nop;                                        \
    b       ExitOtherException;                 \
    nop;


#define SYSCL_EXCEPTION_ENTRY(name)             \
    jal     name;                               \
    nop;                                        \
    b       ExitSysCallException;               \
    nop;


LEAF_ENTRY(OtherExceptionTable)

    .set    noreorder
    .set    noat

    OTHER_EXCEPTION_ENTRY( InterruptException )
    OTHER_EXCEPTION_ENTRY( TLBModificationException )
    OTHER_EXCEPTION_ENTRY( TLBRefillLoadException )
    OTHER_EXCEPTION_ENTRY( TLBRefillStoreException )
    OTHER_EXCEPTION_ENTRY( AddressErrorLoadException )
    OTHER_EXCEPTION_ENTRY( AddressErrorStoreException )
    OTHER_EXCEPTION_ENTRY( BusErrorLoadException )
    OTHER_EXCEPTION_ENTRY( BusErrorStoreException )
    SYSCL_EXCEPTION_ENTRY( SysCallException )
    OTHER_EXCEPTION_ENTRY( BreakPointException )
    OTHER_EXCEPTION_ENTRY( ReservedInstructionException )
    OTHER_EXCEPTION_ENTRY( CoprocessorUnusableException )
    OTHER_EXCEPTION_ENTRY( ArithmeticOverflowException )
    OTHER_EXCEPTION_ENTRY( TrapException )
    OTHER_EXCEPTION_ENTRY( ReservedException )
    OTHER_EXCEPTION_ENTRY( FloatingPointException )
    OTHER_EXCEPTION_ENTRY( ReservedException )
    OTHER_EXCEPTION_ENTRY( ReservedException )
    OTHER_EXCEPTION_ENTRY( ReservedException )
    OTHER_EXCEPTION_ENTRY( ReservedException )
    OTHER_EXCEPTION_ENTRY( ReservedException )
    OTHER_EXCEPTION_ENTRY( ReservedException )
    OTHER_EXCEPTION_ENTRY( ReservedException )
    OTHER_EXCEPTION_ENTRY( WatchException )
    OTHER_EXCEPTION_ENTRY( ReservedException )
    OTHER_EXCEPTION_ENTRY( ReservedException )
    OTHER_EXCEPTION_ENTRY( ReservedException )
    OTHER_EXCEPTION_ENTRY( ReservedException )
    OTHER_EXCEPTION_ENTRY( ReservedException )
    OTHER_EXCEPTION_ENTRY( ReservedException )
    OTHER_EXCEPTION_ENTRY( ReservedException )
    OTHER_EXCEPTION_ENTRY( ReservedException )



ALTERNATE_ENTRY(ExitOtherException)

    lw      v0,v0RegTable(sp)
    lw      v1,v1RegTable(sp)

ALTERNATE_ENTRY(ExitSysCallException)


    lw      t1,t1RegTable(sp)
    lw      t2,t2RegTable(sp)
    lw      t3,t3RegTable(sp)
    lw      t4,t4RegTable(sp)
    lw      t5,t5RegTable(sp)
    lw      t6,t6RegTable(sp)
    lw      t7,t7RegTable(sp)
    lw      t8,t8RegTable(sp)
    lw      t9,t9RegTable(sp)
    lw      t0,t0RegTable(sp)
    lw      AT,atRegTable(sp)
    lw      a0,a0RegTable(sp)
    lw      a1,a1RegTable(sp)
    lw      a2,a2RegTable(sp)
    lw      a3,a3RegTable(sp)
    lw      k0,k0RegTable(sp)
    lw      k1,k1RegTable(sp)
    lw      gp,gpRegTable(sp)
    lw      ra,raRegTable(sp)

    lw      sp,spRegTable(sp)

    eret
    nop

    .end    OtherExceptionTable


/////////////////////////////////////////////////////////////////
//
// Interrupt exception
//
// Note: t1 contains the copy of cause register.
//

LEAF_ENTRY(InterruptException)

    .set    noreorder

    srl     t2,t1,5                     // move IP(3:0) bits to [6:3]
    la      t3,IPTable                  // get IP table base address
    andi    t2,t2,0x0078                // pick IP(3:0)
    addu    t2,t3,t2

    jalr    t2                          // jump to the IP routine
    srl     t2,t1,9                     // move IP(7:4) bits to [6:3]
    b       ExitOtherException
    nop

IPTable:
    j       MoreIPChk
    andi    t2,t2,0x0078                // pick IP(7:4)

    j       SoftwareInterrupt0          // 0001
    nop

    j       SoftwareInterrupt1          // 0010
    nop