startup.s
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· S 代码 · 共 965 行 · 第 1/2 页
S
965 行
/*++
Copyright (c) 1997 Microsoft Corporation
Module Name:
startup.s
Abstract:
CPU startup initialization rotuine
Author:
Jun Liu 01-Jul-1996
Environment:
Kernel mode
History:
sudhakar kanuri 00-Jan-20 modified cache routines for vr5432
Bob Fries 15-Apr-98 Added support for 8Mb memory config for EMB1
Note:
--*/
#define ASSEMBLY_LANGUAGE
#include "kxmips.h"
#include "alt_def.h"
#include "romdef.h"
#include "vrc5074.h"
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Routine Description:
This routine will provide the jump vectors located
at the targets of the processor exception vectors.
N.B. This routine must be located at the start of ROM which
is the location of the reset vector, since it also serves as
the entry point after the reset.
Arguments:
None.
Return Value:
None.
--*/
LEAF_ENTRY(ResetEntryPoint)
.set noreorder
/////////////////////////////////////////////////////////////////
//
// ROM Serivce Routine Entry Table
//
// This part of instructions must be loaded at location 0x0 in the
// rom. This will appear as BFC00000 (virtual) to the processor.
// The first part code is a jump table for rom routines that other
// programs can call. They are placed here so that they will be
// unlikely to move.
//
// Note: To find the entry x, use PROM_ENTRY(x) macro.
//
b ResetException
li k0,BF_COLDBOOT
// BOSTON does not require the modification below
/////////////////////////////////////////////////////////////////
//
// Major Kludge to get Altoona to boot from flash.
// At reset, 1fc00000 space is bytewide which works fine for ROM
// But the flash are 4 bytes wide. Thus accesses to flash
// only return every fourth byte.
// To fix, the following code will hardcode opcodes into every forth
// byte to modify the register that controls this and then jump back to
// the reset exception vector and try again.
//
// 3c08bfa0 lui t0,0xBFA0
// 3c091fc0 lui t1,0x1FC0
// 3529009d ori t1,t1,0x009D
// ad090078 sw t1,0x78(t0)
// 1000fff9 b ResetEntryPoint
// 8d090078 lw t1,0x78(t0)
.word 0x00000000
.word 0x00000000
.word 0x000000a0
.word 0x000000bf
.word 0x00000008
.word 0x0000003c
.word 0x000000c0
.word 0x0000001f
.word 0x00000009
.word 0x0000003c
.word 0x0000009d
.word 0x00000000
.word 0x00000029
.word 0x00000035
.word 0x00000078
.word 0x00000000
.word 0x00000009
.word 0x000000ad
.word 0x000000f9
.word 0x000000ff
.word 0x00000000
.word 0x00000010
.word 0x00000078
.word 0x00000000
.word 0x00000009
.word 0x0000008d
#if 0
/////////////////////////////////////////////////////////////////
//
.space PROM_ENTRY(16) - PROM_ENTRY(1)
//
// Following section is filled by the ROM packaging utility.
//
.word 0x0 // (16): Revision
.word 0x0 // (17): Day, month and year
.word 0x0 // (18): GUIDLo
.word 0x0 // (19): GUIDHi
#endif
/////////////////////////////////////////////////////////////////
//
// Default Kernel Page Table Array
//
// This array is a data structure that stores virtual-to-physical
// address translation right after the power. Althought, it may
// use use a different table after OS starts, the wired entry
// will stay forever.
//
PTEArray:
#if 0
// IO space
PTE( IO_BASE,
IO_VIRTUAL,
0,
PAGE_UNCACHED,
PAGE_DIRTY,
PAGE_VALID,
PAGE_GLOBAL,
IO_PAGEMASK )
// Interrupt ackknowledge space
PTE( INTERRUPT_ACK_BASE,
INTERRUPT_ACK_VIRTUAL,
0,
PAGE_UNCACHED,
PAGE_DIRTY,
PAGE_VALID,
PAGE_GLOBAL,
INTERRUPT_ACK_PAGEMASK )
// PCI config I/O space
PTE( PCICONFIG_BASE,
PCICONFIG_VIRTUAL,
0,
PAGE_UNCACHED,
PAGE_DIRTY,
PAGE_VALID,
PAGE_GLOBAL,
PCICONFIG_PAGEMASK )
#endif
EndOfWired:
EndOfPTEArray:
//
// The program should never reach here
//
XResetEntryPoint:
j XResetEntryPoint
nop
.end ResetEntryPoint
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Routine Description:
This routine will initialize the TLB for virtual addressing.
It sets the TLB according to a table of TLB entries. All other
unused TLB entries will be zeroed and therefore invalidated.
N.B. This routine must be loaded in the first page of the rom
and must be called using BFC00XXXX addresses.
Arguments:
None.
Return Value:
None.
Revision History:
--*/
LEAF_ENTRY(TlbInit)
//
// zero the whole TLB
//
li t0,0x18
mtc0 t0,entrylo0 // tag data to store
mtc0 t0,entrylo1
nop
li t0,KSEG1_BASE // set entry hi
mtc0 zero,pagemask
mtc0 t0,entryhi
move t9,zero // tlb entry index
li t0,TB_SIZE // get last index
mtc0 t9,index // entry pointer
TlbClrLp:
addiu t9,t9,1 // increment counter
tlbwi // store it
bne t9,t0,TlbClrLp // loop if less than max entries
mtc0 t9,index // entry pointer
//
// Initialize TLB from PTE array
//
la t9,ResetEntryPoint
la t7,PTEArray
la t8,EndOfWired
la t1,PTEArray+PROM_BASE
la t2,EndOfPTEArray+PROM_BASE
subu t1,t1,t9
subu t2,t2,t9
subu t7,t8,t7
beq zero,t7,NoTlbLp // skip loop if no PTE entries
move t9,zero
div t7,t7,PTE_EntrySize // compute the No. of wired entries
LoadTlbLp:
lw t3,PTE_EntryHi(t1) // read entryhi from PTE
lw t4,PTE_EntryLo0(t1) // read entrylo0 from PTE
lw t5,PTE_EntryLo1(t1) // read entrylo1 from PTE
lw t6,PTE_PageMask(t1) // read pagemask from PTE
mtc0 t3,entryhi // write entryhi
mtc0 t4,entrylo0 // write entrylo0
mtc0 t5,entrylo1 // write entrylo1
mtc0 t6,pagemask // write pagemask
mtc0 t9,index // write index
addiu t1,t1,PTE_EntrySize // set pointer to next entry
tlbwi // write tlb entry
bne t1,t2,LoadTlbLp // if not last go for next
addiu t9,t9,1 // increment index for next tlb entry
NoTlbLp:
mtc0 t7,wired // Setup wired register
j ra // return
nop
.end TlbInit
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Routine Description:
This routine invalidates the contents of the instruction cache.
The instruction cache is invalidated by writing an invalid tag to
each cache line, therefore nothing is written back to memory.
Arguments:
None.
Return Value:
None.
--*/
LEAF_ENTRY(InvalidateICache)
//
// invalid state
//
mtc0 zero,taglo
mtc0 zero,taghi
li t0,0x80103fe0
li t1,0x80100000
//
// store tag to all icache lines
//
WriteICacheTag:
cache INDEX_STORE_TAG_I,0(t0) // store tag in Instruction cache
nop
nop
cache INDEX_STORE_TAG_I,1(t0) // store tag in Instruction cache
nop
nop
bne t0,t1,WriteICacheTag // loop
addiu t0,t0,-0x20
nop
j ra
nop
.end InvalidateICache
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Routine Description:
This routine invalidates the contents of the D cache.
Data cache is invalidated by writing an invalid tag to each cache
line, therefore nothing is written back to memory.
Arguments:
None.
Return Value:
None.
--*/
LEAF_ENTRY(InvalidateDCache)
//
// invalid state
//
mtc0 zero,taglo
mtc0 zero,taghi
li t0,0x80103fe0
li t1,0x80100000
//
// store tag to all Dcache
//
WriteDCacheTag:
cache INDEX_STORE_TAG_D,0(t0) // store tag in Data cache
nop
nop
cache INDEX_STORE_TAG_D,1(t0) // store tag in Data cache
nop
nop
bne t0,t1,WriteDCacheTag // loop
addiu t0,t0,-0x20
nop
j ra
nop
.end InvalidateDCache
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Routine Description:
This routine invalidates the contents of the secondary cache.
The secondary cache is invalidated by writing an invalid tag to
each cache line, therefore nothing is written back to memory.
Arguments:
None.
Return Value:
None.
--*/
LEAF_ENTRY(InvalidateSCache)
j ra /* XXX: 5464 */
nop
.end InvalidateSCache
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Routine Description:
This routine flushes the whole contents of the Dcache
Arguments:
None.
Return Value:
None.
--*/
LEAF_ENTRY(FlushDCache)
li t0,0x80103fe0
li t1,0x80100000
FlushDCacheTag:
cache INDEX_WRITEBACK_INVALIDATE_D,0(t0) // Invalidate data cache
nop
nop
cache INDEX_WRITEBACK_INVALIDATE_D,1(t0) // Invalidate data cache
nop
nop
bne t0,t1,FlushDCacheTag // loop
addiu t0,t0,-0x20
j ra /* XXX: 5464 */
nop
.end FlushDCache
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Routine Description:
This routine initializes the data fields of the primary and
secondary data caches.
Arguments:
None.
Return Value:
None.
--*/
LEAF_ENTRY(InitDataCache)
// create dirty exclusive to all Dcache
//
mtc1 zero,f0 // zero f0
mtc1 zero,f1 // zero f1
li t0,0x80103fe0
li t1,0x80100000
WriteDCacheDe:
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