startup.s
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· S 代码 · 共 965 行 · 第 1/2 页
S
965 行
cache CREATE_DIRTY_EXCLUSIVE_D,0(t0) // store tag in Data cache
nop
cache CREATE_DIRTY_EXCLUSIVE_D,1(t0) // store tag in Data cache
sdc1 f0,0(t1) // write
sdc1 f0,8(t1) // write
bne t0,t1,WriteDCacheDe // loop
addiu t0,t0,-0x20
nop
j ra // return
nop
.end InitDataCache
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Routine Description:
This routine will initialize the cache tags and data for the
primary data cache, primary instruction cache, and the secondary cache
(if present).
Subroutines are called to invalidate all of the tags in the
instruction and data caches.
Arguments:
None.
Return Value:
None.
--*/
LEAF_ENTRY(CacheInit)
move s0,ra // save ra.
//
// Disable Cache Error exceptions.
//
li t0, (1<<PSR_DE) | (1 << PSR_CU1) | (1 << PSR_BEV)
mtc0 t0,psr
//
// Invalidate the caches
//
bal InvalidateICache
nop
bal InvalidateDCache
nop
//
// Initialize the data cache(s)
//
bal InitDataCache
nop
//
// Fill the Icache, all icache lines
//
li t0,0x80103fe0
li t1,0x80100000
FillICache:
cache INDEX_FILL_I,0(t0) // Fill I cache from memory
nop
cache INDEX_FILL_I,1(t0)
nop
bne t0,t1,FillICache // loop
addiu t0,t0,-0x20 // increment index
//
// Invalidate the caches again
//
bal InvalidateICache
nop
bal InvalidateDCache
nop
NoInvSCache:
//
// Enable cache error exception.
//
li t1, (1 << PSR_CU1) | (1 << PSR_BEV)
mtc0 t1,psr
nop
nop
nop
move ra,s0 // move return address back to ra
j ra // return from routine
nop
.end CacheInit
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Routine Description:
This is the handler for the reset exception. It first checks the cause
of the exception. If it is an NMI, then control is passed to the
exception dispatch routine. Otherwise the machine is initialized.
The basic are:
1) Map the I/O devices.
2) Test the processor.
3) Test the MCTADR
4) Map ROM. Perform a ROM checksum.
5) Test a portion of Memory
6) Test TLB
7) Copy routines to memory
8) Initialize caches
9) Initialize stack for C language calls and other stack operations
10) Copy selftest and firmware code to memory and jump to it.
N.B. This routine must be loaded into the first page of rom.
Arguments:
None.
Return Value:
None.
--*/
LEAF_ENTRY(ResetException)
.set noreorder
//
// Change CPU to little endian mode
//
#if 0
mfc0 k0,config // get the current config register
nop
and k0,k0,~(1<<CONFIG_BE) // clear big endian bit
or k0,k0,(1<<CONFIG_DB) // set d-cache line size
or k0,k0,(1<<CONFIG_IB) // set i-cache line size
and k0,k0,~(0x7<<CONFIG_K0) // kseg0 coherancy algorithm = 0
nop
mtc0 k0,config // setup little endian mode
nop
#else
li k0, 0x00000001
mtc0 k0, config
nop
#endif
//
// Check if it is NMI
//
mfc0 k0,psr // get status register
li k1,(1<<PSR_SR) // bit indicates soft reset.
and k1,k1,k0 // mask PSR with SR bit (k1=0 -> Cold Reset)
beq k1,zero,InitReset // skip below if cold reset
nop
mfc0 k0,psr // get currrent status register
and k0, ~(1 << PSR_IE)
mtc0 k0,psr
or k1,k0,(1<<(PSR_INTMASK+6))
or k1,0x00010000 //disable cache errors
nop
nop
nop
nop
nop
nop
mtc0 k1,psr
nop
nop
nop
nop
nop
nop
nop
mfc0 k0,cause // get cause register
li k1,0x00004000
and k1,k1,k0 // mask IP6 bit (k1!=0 -> NMI)
mfc0 k0,psr // get currrent status register
and k0,~(1<<(PSR_INTMASK+6))
mtc0 k0,psr
beq k1,zero,InitReset
nop
#ifdef BOOT_MONITOR
// fall through if no boot monitor to jump to
la k0,NMIHandle
j k0
nop
#endif
InitReset:
//
// Set Boot Flags
//
li k0,BF_COLDBOOT
ALTERNATE_ENTRY(AlternateReset)
mtc0 k0,compare
#define REG_WRITE64(OFFSET,DATAHI,DATALO) \
li t2,DATAHI ; \
sw t2,OFFSET+4(t0); \
li t2,DATALO; \
sw t2,OFFSET(t0);
//
// Configure Physical Device Address Registers (PDARs)
// Enable memory controller
//
li t0,VRC5074_BASE | KSEG1_BASE
// REG_WRITE64(NILE4_MEMCTRL,0,0x9A)//for 5474 board
REG_WRITE64(NILE4_SDRAM0, 0, 0xba) //for 5476 board
REG_WRITE64(NILE4_MEMCTRL,0,0x92)//for 5476 board
//
// Clean up COP_0 registers
//
li k0, (1<<PSR_BEV) | (1<<PSR_CU1) | (1<<PSR_ERL) | (1<<PSR_FR)
mtc0 zero,watchlo // initialize the watch
mtc0 zero,watchhi // address registers
mtc0 k0,psr // initialize the status register
//
//
// Initialize the TLB.
//
bal TlbInit
nop
//
// Initialize the cache
//
bal CacheInit
nop
//
// Handle Cold Reset
//
ColdReset:
//
// Copy monitor to DRAM
//
li t1, MONITOR_SIZE // get monitor size
li t2, PROM_BASE | KSEG1_BASE // get prom base address
li t3, MONITOR_BASE_ADDRESS // get copy-to base address
addu t0, t2, t1 // compute the end address
CopyMonLp:
lw t4, 0(t2) // get source data 0
lw t5, 4(t2) // get source data 1
lw t6, 8(t2) // get source data 2
lw t7, 12(t2) // get source data 3
addu t2, t2, 16 // increment source counter
sw t4, 0(t3) // copy data 0 to target area
nop
sw t5, 4(t3) // copy data 1 to target area
nop
sw t6, 8(t3) // copy data 2 to target area
nop
sw t7, 12(t3) // copy data 3 to target area
nop
bne t0, t2, CopyMonLp // loop until completes
addu t3, t3, 16 // increment destination counter
//
// Jump to DRAM region and start using TLB
//
la t1, VirtEntry
jr t1
nop
nop
nop
nop
nop
nop
nop
//
// Enter cached DRAM area for execution
//
VirtEntry:
jal InitializeExceptionVector
nop
la t1,ResetEntryPoint // get monitor virtual base address
li t2,0xdfff0000
li t3,MONITOR_SIZE+MONITOR_STACK_SIZE-4-0x100
mfc0 t0,psr // get currrent status register
and t1,t1,t2
and t0,t0,~(1 << PSR_BEV) // clear BEV bit
add t1,t1,t3
move sp,t1
mtc0 t0,psr // exception vectors are in DRAM now
//
// initialize altoona hardware
//
jal AltoonaInit
nop
//
// Get boot flags
//
mfc0 a0,compare
//j main // enter main startup routine
j BootloaderMain // enter main startup routine
nop
.end ResetException
#ifdef BOOT_MONITOR
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Routine Description:
This routine will serve the NMI exception
Arguments:
None.
Return Value:
None.
--*/
LEAF_ENTRY(NMIHandle)
.set noreorder
.set noat
sw sp,(spRegTable-RegisterTableSize)(sp)
subu sp,sp,RegisterTableSize
sw t1,t1RegTable(sp)
sw t2,t2RegTable(sp)
sw t3,t3RegTable(sp)
sw t4,t4RegTable(sp)
sw t5,t5RegTable(sp)
sw t6,t6RegTable(sp)
sw t7,t7RegTable(sp)
sw t8,t8RegTable(sp)
sw t9,t9RegTable(sp)
sw a0,a0RegTable(sp)
sw a1,a1RegTable(sp)
sw a2,a2RegTable(sp)
sw a3,a3RegTable(sp)
sw t0,t0RegTable(sp)
sw AT,atRegTable(sp)
sw v0,v0RegTable(sp)
sw v1,v1RegTable(sp)
sw k0,k0RegTable(sp)
sw k1,k1RegTable(sp)
sw gp,gpRegTable(sp)
sw ra,raRegTable(sp)
jal SaveRegisterInstance
move a0,sp
jal FwMonitor
li a1,NMI_EXCEPTION
jal EnableExtInt
nop
mfc0 k0,psr // get status register
and k1,k0,~( (1<< PSR_BEV) | (1<<PSR_EXL) )
mtc0 k1,psr
lw t0,randomRegTable(sp)
lw t1,indexRegTable(sp)
lw t2,entrylo0RegTable(sp)
lw t3,entrylo1RegTable(sp)
lw t4,contextRegTable(sp)
lw t5,pagemaskRegTable(sp)
lw t6,wiredRegTable(sp)
mtc0 t0,random
mtc0 t1,index
mtc0 t2,entrylo0
mtc0 t3,entrylo1
mtc0 t4,context
mtc0 t5,pagemask
mtc0 t6,wired
lw t0,badvaddrRegTable(sp)
lw t1,countRegTable(sp)
lw t2,entryhiRegTable(sp)
lw t3,compareRegTable(sp)
// lw t4,psrRegTable(sp)
// lw t5,causeRegTable(sp)
lw t6,epcRegTable(sp)
mtc0 t0,badvaddr
mtc0 t1,count
mtc0 t2,entryhi
mtc0 t3,compare
// mtc0 t4,psr
// mtc0 t5,cause
mtc0 t6,epc
lw t0,configRegTable(sp)
lw t1,pridRegTable(sp)
lw t2,lladdrRegTable(sp)
lw t3,watchloRegTable(sp)
lw t4,watchhiRegTable(sp)
lw t5,eccRegTable(sp)
mtc0 t0,config
mtc0 t1,prid
mtc0 t2,lladdr
mtc0 t3,watchlo
mtc0 t4,watchhi
mtc0 t5,ecc
lw t0,tagloRegTable(sp)
lw t1,taghiRegTable(sp)
lw t2,errorepcRegTable(sp)
mtc0 t0,taglo
mtc0 t1,taghi
mtc0 t2,errorepc
li k0,(1<<PSR_EXL)
or k0,k1,k0
mtc0 k0,psr
j ExitOtherException
nop
.end NMIHandle
#endif
#if 1
LEAF_ENTRY(GetSP)
move v0, sp
j ra
nop
.end GetSP
#endif
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