gpevga.h
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//
// Sample MGDI driver (IGS2010)
//
// Copyright (c) 1997,1998 Microsoft Corportaion
//
// ported from IGS2010 driver Dec.1997
#ifndef __GPEVGA_H__
#define __GPEVGA_H__
#include "ioport.h" // definitions of the port classes used here
struct ModeInit;
class GPEVGA;
//
// Class GPEVGA
//
// List of I/O ports which are used to access standard VGA registers
enum EVGAPortIDs{
PortId_3BA,
PortId_3C0,
PortId_3C1,
PortId_3C2,
PortId_3C3,
PortId_3C4,
PortId_3C5,
PortId_3C6,
PortId_3C7,
PortId_3C8,
PortId_3C9,
PortId_3CA,
PortId_3CC,
PortId_3CE,
PortId_3CF,
PortId_3D0,
PortId_3D1,
PortId_3D2,
PortId_3D3,
PortId_3D4,
PortId_3D5,
PortId_3D6,
PortId_3D7,
PortId_3DA,
PortId_46E8,
numVGAPortIDs
};
class GPEVGA : public GPE
{
protected:
PortRange *m_pPortRanges; // Required for ioport.h
Port m_VGAIOPort[numVGAPortIDs]; // All IO ports used by VGA
RWPort8 reg_POS;
RWSplitPort8 reg_MISC; // R:3CC,W:3C2 Miscellaneous output register
RWSplitPort8 reg_FCR_WT; // R:3CA,W:3DA Feature control register
IndexedReg8 reg_SR; // Sequence registers
IndexedReg8 reg_CR; // CRTC registers (and extensions)
IndexedReg8 reg_GR; // Graphics controller registers
FlipIndexedReg8 reg_AR; // Attribute controller registers
IndexedReg8 reg_XR; // Extension registers
IndexedReg8 reg_MR; // Multimedia Registers
unsigned int m_nTicksPerFrame; // E.g. 17 for 60 Hz frames, 1mS ticks
int m_nXHot; // Hot spot for cursor
int m_nYHot;
#ifdef TVOUT
unsigned char *m_pTvRegs; // TV register base
UCHAR m_Reg33; // save location for register
UCHAR m_Reg3C; // save location for register
#endif //TVOUT
public:
GPEVGA(); // Maps in standard VGA ports
void SetVGAMode( ModeInit *pMode );
virtual void WaitForVBlank();
void DetermineScreenRefreshRate();
virtual int InVBlank();
void UnlockVGA();
void LockVGA();
virtual SCODE SetPalette(
const PALETTEENTRY *src,
unsigned short firstEntry,
unsigned short numEntries );
virtual void VBlankReceived() = 0; // Called when VBlank is entered
#ifdef TVOUT
// NTSC TV out support routines
VOID SetTvMode();
VOID SetTVReg(const WORD *wPtr, int iCounter);
USHORT ReadTVReg(WORD index);
VOID WriteTVReg(WORD index, WORD data);
VOID UnlockTVReg(VOID);
VOID LockTVReg(VOID);
VOID EnableTV(BOOLEAN iOnOff);
VOID TVOn(BOOLEAN iOnOff);
VOID SetTVColor();
VOID BypassMode(BOOLEAN iOnOff);
VOID SetInterpolation();
USHORT GetBusWidth(VOID);
#endif //TVOUT
};
// register sizes (they differ on different chip sets)
#define REG_SR_SIZE 0x5
#define REG_GR_SIZE 0x9
#define REG_AR_SIZE 0x15
#define REG_CR_SIZE 0x19
#define REG_XR_SIZE 0x3A
typedef struct _REG_INDEX_DATA {
unsigned char Index; // register index
unsigned char Data; // register data
} REG_INDEX_DATA, *PREG_INDEX_DATA;
struct ModeInit
{
GPEMode gpeMode;
unsigned char Init_SR[REG_SR_SIZE]; // Sequence Registers
unsigned char Init_GR[REG_GR_SIZE]; // Graphic Controller Registers
unsigned char Init_AR[REG_AR_SIZE]; // Attribute Registers
unsigned char Init_CR[REG_CR_SIZE]; // CRT Control Registers
REG_INDEX_DATA Init_XR[REG_XR_SIZE]; // Extension Registers
};
#define NUMVGAMODES 1
#ifdef FB16BPP
#ifndef UNDERSCAN // from IGS Overscan tables
/* mode#0: 640 x 480 16Bpp 60Hz VESA mode 0x111 */
#define INSTANTIATE_MODE_INIT \
ModeInit VGAMode[NUMVGAMODES] = \
{ \
{ \
{ 0, 640,480,16,60, gpe16Bpp }, /* mode#0: 640 x 480 16Bpp 60Hz VESA mode 0x111 */\
{ /* Init_SR */ \
0x00, 0x01, 0x0F, 0x00, 0x0E, \
}, \
{ /* Init_GR */ \
0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x05, 0x0F, \
0xFF \
}, \
{ /* Init_AR */ \
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, \
0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, \
0x01, 0x00, 0x0F, 0x00, 0x00 /*Attr Reg<0-14>*/ \
}, \
{ /* Init_CR */ \
0x5F, 0x4F, 0x4F, 0x81, 0x52, 0x9E, 0x0B, 0x3E, \
0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
0xE9, 0x8B, 0xDF, 0xA0, 0x00, 0xE6, 0x04, 0xC3, \
0xFF, \
}, \
{ /* Init_XR index/data */ \
/* from ExtRegs in IGS sample */ \
0x10, 0x10, \
0x11, 0x00, \
0x12, 0x00, \
0x13, 0x00, \
0x14, 0x51, \
0x15, 0x00, \
0x16, 0x00, \
0x30, 0x00, /*Memory size related*/ \
0x31, 0x00, \
0x32, 0x00, \
0x33, 0x11, \
0x3C, 0x00, \
0x3E, 0x00, \
0x3F, 0x00, \
0x50, 0x00, \
0x51, 0x00, \
0x52, 0x00, \
0x53, 0x00, \
0x54, 0x00, \
0x55, 0x00, \
0x56, 0x00, \
0x57, 0x01, \
0x58, 0x00, \
0x59, 0x00, \
0x5A, 0x00, \
0x5C, 0x00, \
0x5D, 0x00, \
0x5E, 0x00, \
0x5F, 0x00, \
0x70, 0x0B, \
0x71, 0x03, \
0x72, 0x05, /*2 MB, 64 bits*/ \
0x73, 0x30, \
0x74, 0x10, \
0x75, 0x10, \
0x76, 0x00, \
0x77, 0x01, /*8Bpp*/ \
0x78, 0x00, \
0x79, 0x33, /*!!! if Memory Clock < 75 Mhz, 0x79=0x30*/ \
0x7A, 0xC8, \
0x90, 0x03, \
0xB0, 0xD2, /*Pixel Clock = 25.175 MHz*/ \
0xB1, 0xD3, \
0xB2, 0xDB, /*Memory Clock = 75MHz*/ \
0xB3, 0x54, \
0xB5, 0x00, \
0xBA, 0x00, \
0xBB, 0x00, \
0xBF, 0x00, \
0xF8, 0x04, \
/* from IGS 640x480x16 */ \
0xB0, 0xD2, \
0xB1, 0xD3, \
0xBA, 0x00, /*Pixel clock overflow register*/ \
0x11, 0x00, /*ExtRegs*/ \
0x14, 0xA1, \
0x15, 0x00, \
0x56, 0x00, \
0x77, 0x02 \
} \
} \
};
#else //!UNDERCAN
/* IGS UnderScan tables */
/* mode#0: 640 x 480 16Bpp 60Hz VESA mode 0x111 */
#define INSTANTIATE_MODE_INIT \
ModeInit VGAMode[NUMVGAMODES] = \
{ \
{ \
{ 0, 640,480,16,60, gpe16Bpp }, /* mode#0: 640 x 480 16Bpp 60Hz VESA mode 0x111 */\
{ /* Init_SR */ \
0x00, 0x01, 0x0F, 0x00, 0x0E, \
}, \
{ /* Init_GR */ \
0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x05, 0x0F, \
0xFF \
}, \
{ /* Init_AR */ \
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, \
0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, \
0x01, 0x00, 0x0F, 0x00, 0x00 /*Attr Reg<0-14>*/ \
}, \
{ /* Init_CR */ \
0x67, 0x4F, 0x4E, 0x8A, 0x55, 0x9E, 0x3B, 0x3E, \
0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
0xFF, 0x8B, 0xDF, 0xA0, 0x00, 0xDF, 0x0B, 0xC3, \
0xFF, \
}, \
{ /* Init_XR index/data */ \
/* from ExtRegs in IGS sample */ \
0x10, 0x10, \
0x11, 0x00, \
0x12, 0x00, \
0x13, 0x00, \
0x14, 0x51, \
0x15, 0x00, \
0x16, 0x00, \
0x30, 0x00, /*Memory size related*/ \
0x31, 0x00, \
0x32, 0x00, \
0x33, 0x11, \
0x3C, 0x00, \
0x3E, 0x00, \
0x3F, 0x00, \
0x50, 0x00, \
0x51, 0x00, \
0x52, 0x00, \
0x53, 0x00, \
0x54, 0x00, \
0x55, 0x00, \
0x56, 0x00, \
0x57, 0x01, \
0x58, 0x00, \
0x59, 0x00, \
0x5A, 0x00, \
0x5C, 0x00, \
0x5D, 0x00, \
0x5E, 0x00, \
0x5F, 0x00, \
0x70, 0x0B, \
0x71, 0x03, \
0x72, 0x05, /*2 MB, 64 bits*/ \
0x73, 0x30, \
0x74, 0x10, \
0x75, 0x10, \
0x76, 0x00, \
0x77, 0x01, /*8Bpp*/ \
0x78, 0x00, \
0x79, 0x33, /*!!! if Memory Clock < 75 Mhz, 0x79=0x30*/ \
0x7A, 0xC8, \
0x90, 0x03, \
0xB0, 0xD2, /*Pixel Clock = 25.175 MHz*/ \
0xB1, 0xD3, \
0xB2, 0xDB, /*Memory Clock = 75MHz*/ \
0xB3, 0x54, \
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