gpevga.h
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 577 行 · 第 1/2 页
H
577 行
0xB5, 0x00, \
0xBA, 0x00, \
0xBB, 0x00, \
0xBF, 0x00, \
0xF8, 0x04, \
/* from IGS 640x480x16 */ \
0xB0, 0x67, \
0xB1, 0xC2, \
0xBA, 0x1C, /*Pixel clock overflow register*/ \
0x11, 0x00, /*ExtRegs*/ \
0x14, 0xA1, \
0x15, 0x00, \
0x56, 0x00, \
0x77, 0x02, \
}, \
} \
};
#endif //OVERSCAN
#else //FB16BPP
#error("Video buffer depth required, only FB16BPP currently supported");
#endif //FB16BPP
extern ModeInit VGAMode[];
#ifdef TVOUT
#ifdef UNDERSCAN
/* This table is for NTSC 640x480 @60Hz underscan mode */
const USHORT TV640x480x60[] = {
0xE430, 0x0000,
0xE434, 0x0000,
0xE438, 0x3000,
0xE43C, 0x020C,
0xE440, 0x0029,
0xE444, 0x020C,
0xE448, 0x0029,
0xE44C, 0x7038,
0xE450, 0x7878,
0xE454, 0x8009,
0xE458, 0xDE00,
0xE45C, 0x0000,
0xE460, 0x003E,
0xE464, 0x0011,
0xE468, 0x0018,
0xE46C, 0x0027,
0xE470, 0x0045,
0xE474, 0x0067,
0xE478, 0x0328,
0xE47C, 0x007D,
0xE480, 0x020A,
0xE484, 0x0011,
0xE488, 0x020A,
0xE48C, 0x0011,
0xE490, 0x0005,
0xE494, 0x000B,
0xE498, 0x0005,
0xE49C, 0x000B,
0xE4A0, 0x92EC,
0xE4A4, 0x4367,
0xE4A8, 0x0052,
0xE4AC, 0x1020,
0xE4B0, 0x0000,
0xE4B4, 0x0000,
0xE4B8, 0x003F,
0xE4BC, 0x0001,
0xE4C0, 0x02D5,
0xE4C4, 0x0001,
0xE4C8, 0x8700,
0xE4CC, 0x8787,
0xE4D0, 0x8787,
0xE4D4, 0x8787,
0xE4D8, 0x8787,
0xE4DC, 0x8787,
0xE4E0, 0x8787,
0xE4E4, 0x8787,
0xE4E8, 0x0000,
0xE4EC, 0x0000,
0xE4F0, 0x0000,
0xE4F4, 0x0000,
0xE4F8, 0x0000,
0xE4FC, 0x0000,
0xE500, 0x0000,
0xE504, 0x0000,
0xE508, 0x0000,
0xE50C, 0x0000,
0xE510, 0x0000,
0xE514, 0x0000,
0xE518, 0x0000,
0xE51C, 0x0000,
0xE520, 0x0000,
0xE524, 0x0012,
0xE528, 0x0012,
0xE52C, 0x0011
};
#else //UNDERSCAN
// overscan
/* This table is for NTSC 640x480 @60Hz overscan mode */
const USHORT TV640x480x60[] = {
0xE430, 0x0000,
0xE434, 0x0000,
0xE438, 0x3000,
0xE43C, 0x020C,
0xE440, 0x0029,
0xE444, 0x020C,
0xE448, 0x0029,
0xE44C, 0x7038,
0xE450, 0xB5B5, //0x7878
0xE454, 0x8000, //0x8009,
0xE458, 0xE200, //0xDE00,
0xE45C, 0x0000,
0xE460, 0x003A,
0xE464, 0x0000,
0xE468, 0x000C,
0xE46C, 0x001B,
0xE470, 0x0041,
0xE474, 0x0061,
0xE478, 0x030C,
0xE47C, 0x0076,
0xE480, 0x020A,
0xE484, 0x0011,
0xE488, 0x020A,
0xE48C, 0x0011,
0xE490, 0x0005,
0xE494, 0x000B,
0xE498, 0x0005,
0xE49C, 0x000B,
0xE4A0, 0x2D04,
0xE4A4, 0x48CC,
0xE4A8, 0x0052,
0xE4AC, 0x1020,
0xE4B0, 0x0000,
0xE4B4, 0x0000,
0xE4B8, 0x003B,
0xE4BC, 0x0001,
0xE4C0, 0x02AA,
0xE4C4, 0x0001,
0xE4C8, 0x8700,
0xE4CC, 0x8787,
0xE4D0, 0x8787,
0xE4D4, 0x8787,
0xE4D8, 0x8787,
0xE4DC, 0x8787,
0xE4E0, 0x8787,
0xE4E4, 0x8787,
0xE4E8, 0x0000,
0xE4EC, 0x0000,
0xE4F0, 0x0000,
0xE4F4, 0x0000,
0xE4F8, 0x0000,
0xE4FC, 0x0000,
0xE500, 0x0000,
0xE504, 0x0000,
0xE508, 0x0000,
0xE50C, 0x0000,
0xE510, 0x0000,
0xE514, 0x0000,
0xE518, 0x0000,
0xE51C, 0x0000,
0xE520, 0x0000,
0xE524, 0x0001,
0xE528, 0x000E,
0xE52C, 0x000D
};
#endif //UNDERSCAN
/*-----------------------------------------------------------------
640x480x60 interpolation
-----------------------------------------------------------------*/
/*REG 3CE*/
const BYTE I640x480x60_3CE[] = {
0xAE, 0x01,
0x5E, 0x32,
/* 0x5D, 0xD4, */
0xA6, 0x08,
0xAB, 0x20,
0xF1, 0x80,
0xDD, 0x02
};
/*REG 3D4*/
const BYTE I640x480x8x60_3D4[] = {
0x40, 0xC0, /* 0x3C0 = 960 = x_ext * (3d4_44<7..4>+1) / 4 */
0x41, 0x03,
0x42, 0x00,
0x43, 0x51, /* 0x51 = 81 = x_ext * bpp / ( (3ce_72<2>==1) ? 8 : 4) + 1*/
/* 0x44, 0x59, = 5,9: skip the 6th line of every 10 lines. */
0x45, 0x97, /* = interpolation on */
0x46, 0x40, /* 0x640 = 1600 = x_ext * (3d4_44<3..0>+1) / 4 */
0x47, 0x06
};
const BYTE I640x480x16x60_3D4[] = {
0x40, 0x80,
0x41, 0x07,
0x42, 0x00,
0x43, 0xA1,
/* 0x44, 0x59, */
0x45, 0x97,
0x46, 0x80,
0x47, 0x0C
};
#endif //TVOUT
// Direct access IO mapped registers
#define reg_AR_ADDR (PORT_RW_8 m_VGAIOPort[PortId_3C0 ]) //Select AR0..14. On Writes, sets 3C0[write]->ATR_DATA
#define reg_AR_DATA (PORT_RW_8 m_VGAIOPort[PortId_3C1 ]) //Read/Write AR0..14 On Writes, sets 3C0[write]->ATR_AD
#define reg_AR_RESET (PORT_RO_8 m_VGAIOPort[PortId_3DA ]) //Reset flip flop to set3CO[write]->ATR_AD
#define reg_CR_ADDR (PORT_RW_8 m_VGAIOPort[PortId_3D4 ]) //Select CR0..CR24
#define reg_CR_DATA (PORT_RW_8 m_VGAIOPort[PortId_3D5 ]) //Read/Write CR0..CR24
#define reg_XR_ADDR (PORT_RW_8 m_VGAIOPort[PortId_3CE ]) //Select XR0..XRFF
#define reg_XR_DATA (PORT_RW_8 m_VGAIOPort[PortId_3CF ]) //Read/Write XR0..XRFF
#define reg_MR_WRITE (PORT_WO_8 m_VGAIOPort[PortId_3C2 ]) // MISC register
#define reg_MR_READ (PORT_RO_8 m_VGAIOPort[PortId_3CC ])
#define reg_DAC_AD_MK (PORT_RW_8 m_VGAIOPort[PortId_3C6 ]) //Pixel read mask (put FF here!)
#define reg_DAC_DATA (PORT_RW_8 m_VGAIOPort[PortId_3C9 ]) //Access palette entry (use 3 times)
#define reg_DAC_RD_AD (PORT_WO_8 m_VGAIOPort[PortId_3C7 ]) //Read index into palette (auto-incr)
#define reg_DAC_STS (PORT_RO_8 m_VGAIOPort[PortId_3C7 ]) //DAC status - checks palette state
#define reg_DAC_WR_AD (PORT_WO_8 m_VGAIOPort[PortId_3C8 ]) //Write index into palette (auto-incr)
#define reg_GR_ADDR (PORT_RW_8 m_VGAIOPort[PortId_3CE ]) //Select GR0..8
#define reg_GR_DATA (PORT_RW_8 m_VGAIOPort[PortId_3CF ]) //Access GR0..8
#define reg_SR_ADDR (PORT_RW_8 m_VGAIOPort[PortId_3C4 ]) //Select SR0..18
#define reg_SR_DATA (PORT_RW_8 m_VGAIOPort[PortId_3C5 ]) //Read/Write SR0..18
#define reg_STATUS_0 (PORT_RO_8 m_VGAIOPort[PortId_3C2 ]) //CRT Irq Pending
#define reg_STATUS_1 (PORT_RO_8 m_VGAIOPort[PortId_3DA ]) //VSync Status
// Indexed registers and their aliases
#define reg_RST_SYNC reg_SR[0x0] // R/W reset - UNUSED!
#define reg_CLK_MODE reg_SR[0x1] // R/W dot clk, chr clk, screen_off
#define reg_EN_WT_PL reg_SR[0x2] // R/W enable cpu mem writes
#define reg_CH_FONT_SL reg_SR[0x3] // R/W font select
#define reg_MEM_MODE reg_SR[0x4] // R/W Mem access control
#define reg_UNLK_EXSR reg_SR[0x8] // R/W Enable SR9..SR18
#define reg_H_TOTAL reg_CR[0x0] // R/W Total character clocks per line
#define reg_H_D_END reg_CR[0x1] // R/W Active char clocks per line
#define reg_S_H_BLANK reg_CR[0x2] // R/W Char no of start of blank period
#define reg_E_H_BLANK reg_CR[0x3] // R/W End hBlank and display skew
#define reg_S_H_SY_P reg_CR[0x4] // R/W Start horizontal sync position
#define reg_E_H_SY_P reg_CR[0x5] // R/W End horizontal sync position
#define reg_V_TOTAL reg_CR[0x6] // R/W Vertical total in scan lines
#define reg_OVFL_REG reg_CR[0x7] // R/W Overflow reg - bit 8 &9抯 of CR6,12,10,15,18
#define reg_P_R_SCAN reg_CR[0x8] // R/W Preset row scan - for soft scrolling
#define reg_MAX_S_LN reg_CR[0x9] // R/W Scan lines / char -1, Bit 9 of CR15,18. Double-scan enable
#define reg_CSSL reg_CR[0xA] // R/W Cursor start row
#define reg_CESL reg_CR[0xB] // R/W Cursor end row
#define reg_STA_H reg_CR[0xC] // R/W Start addr high
#define reg_STA_L reg_CR[0xD] // R/W Start addr low
#define reg_CLA_H reg_CR[0xE] // R/W Cursor addr high
#define reg_CLA_L reg_CR[0xF] // R/W Cursor addr low
#define reg_VRS reg_CR[0x10] // R/W Vertical retrace start
#define reg_VRE reg_CR[0x11] // R/W Vertical retrace end
#define reg_VDE reg_CR[0x12] // R/W Vertical display end
#define reg_SCREEN_OFFSET reg_CR[0x13] // R/W Screen pitch / 2,4,or8 - see CR51
#define reg_ULL reg_CR[0x14] // R/W Underline row & char count mode
#define reg_SVB reg_CR[0x15] // R/W Start vertical blank
#define reg_EVB reg_CR[0x16] // R/W End vertical blank
#define reg_CRT_MD reg_CR[0x17] // R/W CRTC mode, and sync disable
#define reg_LCM reg_CR[0x18] // R/W Split screen address
#define reg_GCCL reg_CR[0x22] // R CPU Latch 0..3 [via GR4 1:0]
#define reg_ATC_F reg_CR[0x24] // R Attribute controller index
#define reg_SET_RST_DT reg_GR[0x0] // R/W Value written in write modes 0 & 3
#define reg_EN_S_R_DT reg_GR[0x1] // R/W Bit write enables for write mode 0
#define reg_COLOR_CMP4Bpp reg_GR[0x2] // R/W Color compare for read mode 1
#define reg_WT_ROP reg_GR[0x3] // R/W Raster op & rotate for writes
#define reg_RD_PL_SL reg_GR[0x4] // R/W Read plane select (0..3)
#define reg_GRP_MODE reg_GR[0x5] // R/W Select write mode (0..3), enable read compare, odd/even, and 256-color support
#define reg_MISC_GM reg_GR[0x6] // R/W Text/graphics & Memory addr range
#define reg_CMP_DNTC reg_GR[0x7] // R/W Color don抰 care bits for read mode 1
#define reg_BIT_MASK reg_GR[0x8] // R/W Write mask
#define reg_PLT_REG reg_AR // R/W 16 6-bit palette registers
#define reg_ATR_MODE reg_AR[0x10] // R/W Attribute mode control
#define reg_BDR_CLR reg_AR[0x11] // R/W Border color 8-bit PA modes only
#define reg_DISP_PLN reg_AR[0x12] // R/W Color plane enable
#define reg_H_PX_PAN reg_AR[0x13] // R/W Horiz pixel panning
#define reg_PX_PAD reg_AR[0x14] // R/W Pixel padding (converts to 8Bpp)
#endif // __GPEVGA_H__
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