rsbuffer.vhd

RS的编码。最新的移动多媒体应用技术的源代码

-- ================================================================================
-- File: RSbuffer.vhd
-- Version: v1.1
-- Author: olivercamel
-- Date: 4.24.2006
-- Description:
-- This module is a buffer designd for R-S encoder. Since the length of output of
-- R-S encoder is 6 words and the requirement input length of Interleaver is 36
-- words at least, a buffer is used to collect the results of R-S encoder's output
-- and then send to Interleaver. A fifo with 4 bit and 64 words generated by IP 
-- toolbench is contained in this RSbuffer. RSbuffer do not require sink_sop and
-- sink_eop signals.
-- Revision History:
-- v1.1, 4.26.2006, add synchronization of inputData and sink_val
-- ================================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- ================================================================================

entity RSbuffer is
	port
	(
		-- clock input
		clk: in std_logic;
		-- asynchroism clear input
		aclr: in std_logic;
		-- 4bit width Data ports
		inputData: in std_logic_vector (3 downto 0);
		outputData: out std_logic_vector (3 downto 0);
		-- simple ALTERA Atlantic interface ports
		sink_val: in std_logic;
		sink_ena: out std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end RSbuffer;

-- ================================================================================

architecture structure of RSbuffer is

-- --------------------------------------------------------------------------------

-- component declaration
-- generate by ALTERA ip toolbench
-- name: fifo_RSbuffer
-- size: 4bit * 64words
component fifo_RSbuffer
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdreq		: IN STD_LOGIC ;
		wrreq		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		usedw		: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
	);
end component;

-- signals those connect to FIFO
signal readRequest: std_logic;
signal usedWidth: std_logic_vector (5 downto 0);
-- usedWidth convert into integer
signal usedwInteger: integer;

-- delayed input signals
signal inputData_d: std_logic_vector (3 downto 0);
signal sink_val_d: std_logic;

-- interval output data
signal interval_outputData: std_logic_vector (3 downto 0);

-- signals those used to Atlantic interface outputs
signal interval_source_val: std_logic;
signal interval_source_sop: std_logic;
signal interval_source_eop: std_logic;
signal interval_sink_ena: std_logic;

-- count signal
signal count: integer range 0 to 36;

-- --------------------------------------------------------------------------------

begin

-- --------------------------------------------------------------------------------

-- synchronize input datas using falling edge
process(clk,inputData,sink_val)
begin
	if falling_edge(clk) then -- using falling edge
		inputData_d <= inputData;
		sink_val_d <= sink_val;
	end if;
end process;

-- fifo ports map
u1: fifo_RSbuffer port map
	(
		clock => clk, aclr => aclr,
		data => inputData_d, q => interval_outputData,
		rdreq => readRequest, wrreq => sink_val_d,
		usedw => usedWidth
	);

-- convert std_logic_vector into integer
usedwInteger <= to_integer(unsigned(usedWidth));

-- detect capacity of fifo and set sink_ena
process(clk,usedwInteger)
begin
	if rising_edge(clk) then
		if usedwInteger >= 58 then
			interval_sink_ena <= '0';
		else
			interval_sink_ena <= '1';
		end if;
	end if;
end process;

-- control readRequest and count used to read from fifo
process(aclr,clk,usedwInteger,count)
begin
	if aclr = '1' then
		count <= 0;
		readRequest <= '0';
	else
		if rising_edge(clk) then
			if usedwInteger >= 36 then
				if source_ena = '1' then
					if count <= 0 then
						count <= 1;
						readRequest <= '1';
					elsif count = 36 then
						count <= 0;
						readRequest <= '0';
					else
						count <= count + 1;
						readRequest <= '1';			
					end if;
				else
					readRequest <= '0';
				end if;
			else
				if source_ena = '1' then
					if count = 0 then
						count <= 0;
						readRequest <= '0';
					elsif count = 36 then
						count <= 0;
						readRequest <= '0';
					else
						count <= count + 1;
						readRequest <= '1';			
					end if; 
				else
					readRequest <= '0';
				end if;
			end if;
		end if;
	end if;
end process;

-- generate interface signals
process(aclr,clk,count)
begin
	if aclr = '1' then
		interval_source_val <= '0';
		interval_source_sop <= '0';
		interval_source_eop <= '0';
	else
		if rising_edge(clk) then
			if count = 1 then
				interval_source_sop <= '1';
			else
				interval_source_sop <= '0';
			end if;
			if count = 36 then
				interval_source_eop <= '1';
			else
				interval_source_eop <= '0';
			end if;
			if count = 0 then
				interval_source_val <= '0';
			else
				interval_source_val <= '1';
			end if;
		end if;
	end if;
end process;

-- synchonize output signals using falling edge
process(clk,interval_outputData,interval_source_val,
		interval_source_sop,interval_source_eop,interval_sink_ena)
begin
	if falling_edge(clk) then -- using falling edge
		outputData <= interval_outputData;
		source_val <= interval_source_val;
		source_sop <= interval_source_sop;
		source_eop <= interval_source_eop;
		sink_ena <= interval_sink_ena;
	end if;
end process;

-- --------------------------------------------------------------------------------

end structure;

-- ================================================================================