ofdm.vhd

RS的编码。最新的移动多媒体应用技术的源代码

signal source_sop_DeConstellation: std_logic;
signal source_eop_DeConstellation: std_logic;

-- Zero remover
component ZeroRemove
	port
	(
		clk: in std_logic;
		aclr: in std_logic;
		inputData: in std_logic_vector (3 downto 0);
		outputData: out std_logic_vector (3 downto 0);
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end Component;
signal outputData_ZeroRemove: std_logic_vector (3 downto 0);
signal source_ena_ZeroRemove: std_logic;
signal source_val_ZeroRemove: std_logic;
signal source_sop_ZeroRemove: std_logic;
signal source_eop_ZeroRemove: std_logic;

-- De-Interleaver
component DeInterleaver
	port
	(
		clk: in std_logic;
		aclr: in std_logic;
		inputData: in std_logic_vector (3 downto 0);
		outputData: out std_logic_vector (3 downto 0);
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		sink_ena: out std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end component;
signal outputData_DeInterleaver: std_logic_vector (3 downto 0);
signal source_ena_DeInterleaver: std_logic;
signal source_val_DeInterleaver: std_logic;
signal source_sop_DeInterleaver: std_logic;
signal source_eop_DeInterleaver: std_logic;

-- RS decoder buffer
component RSdecoderbuffer
	port
	(
		clk: in std_logic;
		aclr: in std_logic;
		inputData: in std_logic_vector (3 downto 0);
		outputData: out std_logic_vector (3 downto 0);
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		sink_ena: out std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end component;
signal outputData_RSdecoderbuffer: std_logic_vector (3 downto 0);
signal source_ena_RSdecoderbuffer: std_logic;
signal source_val_RSdecoderbuffer: std_logic;
signal source_sop_RSdecoderbuffer: std_logic;
signal source_eop_RSdecoderbuffer: std_logic;

-- Reed-Solomon Decoder
component RSdecoder
	PORT (
		clk	: IN STD_LOGIC;
		reset	: IN STD_LOGIC;
		rsin	: IN STD_LOGIC_VECTOR (4 DOWNTO 1);
		sink_val	: IN STD_LOGIC;
		sink_sop	: IN STD_LOGIC;
		sink_eop	: IN STD_LOGIC;
		source_ena	: IN STD_LOGIC;
		bypass	: IN STD_LOGIC;
		rsout	: OUT STD_LOGIC_VECTOR (4 DOWNTO 1);
		sink_ena	: OUT STD_LOGIC;
		source_val	: OUT STD_LOGIC;
		source_sop	: OUT STD_LOGIC;
		source_eop	: OUT STD_LOGIC;
		decfail	: OUT STD_LOGIC;
		num_err_sym	: OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
	);
end component;
signal outputData_RSdecoder: std_logic_vector (3 downto 0);
signal source_ena_RSdecoder: std_logic;
signal source_val_RSdecoder: std_logic;
signal source_sop_RSdecoder: std_logic;
signal source_eop_RSdecoder: std_logic;

-- System Output Buffer
component Outputbuffer
	port
	(
		clk: in std_logic;
		aclr: in std_logic;
		inputData: in std_logic_vector (3 downto 0);
		outputData: out std_logic_vector (3 downto 0);
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		sink_ena: out std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end component;

-- --------------------------------------------------------------------------------

begin

-- --------------------------------------------------------------------------------

u1: RSencoder port map
	(
		clk => clock, reset => reset,
		rsin => inputData, rsout => rsout_RSencoder,
		sink_ena => sink_ena, source_ena => source_ena_RSencoder,
		sink_val => sink_val, source_val => source_val_RSencoder,
		sink_sop => sink_sop,
		sink_eop => sink_eop
	);

u2: RSbuffer port map
	(
		clk => clock, aclr => reset,
		inputData => rsout_RSencoder, outputData => outputData_RSbuffer,
		sink_ena => source_ena_RSencoder, source_ena => source_ena_RSbuffer,
		sink_val => source_val_RSencoder, source_val => source_val_RSbuffer,
		                                  source_sop => source_sop_RSbuffer,
		                                  source_eop => source_eop_RSbuffer
	);

u3: Interleaver port map
	(
		clk => clock, aclr => reset,
		inputData => outputData_RSbuffer, outputData => outputData_Interleaver,
		sink_ena => source_ena_RSbuffer, source_ena => source_ena_Interleaver,
		sink_val => source_val_RSbuffer, source_val => source_val_Interleaver,
		sink_sop => source_sop_RSbuffer, source_sop => source_sop_Interleaver,
		sink_eop => source_eop_RSbuffer, source_eop => source_eop_Interleaver
	);

u4: Stuff port map
	(
		clk => clock, aclr => reset,
		inputData => outputData_Interleaver, outputData => outputData_Stuff,
		sink_ena => source_ena_Interleaver, source_ena => source_ena_Stuff,
		sink_val => source_val_Interleaver, source_val => source_val_Stuff,
		sink_sop => source_sop_Interleaver, source_sop => source_sop_Stuff,
		sink_eop => source_eop_Interleaver, source_eop => source_eop_Stuff
	);

u5: Constellation port map
	(
		clk => clock, aclr => reset,
		inputData => outputData_Stuff, outputReal => outputReal_Constellation,
		                               outputImag => outputImag_Constellation,
		sink_ena => source_ena_Stuff, source_ena => source_ena_Constellation,
		sink_val => source_val_Stuff,
		sink_sop => source_sop_Stuff, source_sop => source_sop_Constellation,
		sink_eop => source_eop_Stuff
	);

u6: IFFTcore port map
	(
		clk => clock, reset => reset,
		data_real_in => outputReal_Constellation, fft_real_out => outputReal_IFFT,
		data_imag_in => outputImag_Constellation, fft_imag_out => outputImag_IFFT,
		inv_i => '1',
		-- sink part
		master_sink_ena => source_ena_Constellation,
		master_sink_dav => '1',
		master_sink_sop => source_sop_Constellation,
		-- source part
		master_source_dav => '1',
		master_source_ena => source_val_IFFT,
		master_source_sop => source_sop_IFFT,
		master_source_eop => source_eop_IFFT
	);

u7: CPreal port map
	(
		clk => clock, aclr => reset,
		inputData => outputReal_IFFT, outputData => outputReal_CP,
		                              source_ena => '1',
		sink_val => source_val_IFFT, source_val => source_val_CP,
		sink_sop => source_sop_IFFT,
		sink_eop => source_eop_IFFT

	);

u8: CPimag port map
	(
		clk => clock, aclr => reset,
		inputData => outputimag_IFFT, outputData => outputImag_CP,
		                              source_ena => '1',
		sink_val => source_val_IFFT,
		sink_sop => source_sop_IFFT,
		sink_eop => source_eop_IFFT

	);

u9: CPremoveReal port map
	(
		clk => clock, aclr => reset,
		inputData => outputReal_CP, outputData => outputReal_CPR,
		                           source_ena => source_ena_CPR,
		sink_val => source_val_CP,
		                           source_sop => source_sop_CPR
	);

u10: CPremoveImag port map
	(
		clk => clock, aclr => reset,
		inputData => outputImag_CP, outputData => outputImag_CPR,
		                           source_ena => source_ena_CPR,
		sink_val => source_val_CP
	);

u11: FFTcore port map
	(
		clk => clock, reset => reset,
		data_real_in => outputReal_CPR, fft_real_out => outputReal_FFT,
		data_imag_in => outputImag_CPR, fft_imag_out => outputImag_FFT,
		inv_i => '0',
		-- sink part
		master_sink_ena => source_ena_CPR,
		master_sink_dav => '1',
		master_sink_sop => source_sop_CPR,
		-- source part
		master_source_dav => '1',
		master_source_ena => source_val_FFT,
		master_source_sop => source_sop_FFT,
		master_source_eop => source_eop_FFT
	);

u12: FFTscale port map
	(
		clk => clock,
		inputReal => outputReal_FFT, outputReal => outputReal_FFTscale,
		inputImag => outputImag_FFT, outputImag => outputImag_FFTscale,
		sink_val => source_val_FFT, source_val => source_val_FFTscale,
		sink_sop => source_sop_FFT, source_sop => source_sop_FFTscale,
		sink_eop => source_eop_FFT, source_eop => source_eop_FFTscale
	);

u13: DeConstellation port map
	(
		clk => clock,
		inputReal => outputReal_FFTscale, outputData => outputData_DeConstellation,
		inputImag => outputImag_FFTscale,
		sink_val => source_val_FFTscale, source_val => source_val_DeConstellation,
		sink_sop => source_sop_FFTscale, source_sop => source_sop_DeConstellation,
		sink_eop => source_eop_FFTscale, source_eop => source_eop_DeConstellation
	);

u14: ZeroRemove port map
	(
		clk => clock, aclr => reset,
		inputData => outputData_DeConstellation, outputData => outputData_ZeroRemove,
		                                        source_ena => source_ena_ZeroRemove,
		sink_val => source_val_DeConstellation, source_val => source_val_ZeroRemove,
		sink_sop => source_sop_DeConstellation, source_sop => source_sop_ZeroRemove,
		sink_eop => source_eop_DeConstellation, source_eop => source_eop_ZeroRemove
	);

u15: DeInterleaver port map
	(
		clk => clock, aclr => reset,
		inputData => outputData_ZeroRemove, outputData => outputData_DeInterleaver,
		sink_ena => source_ena_ZeroRemove, source_ena => source_ena_DeInterleaver,
		sink_val => source_val_ZeroRemove, source_val => source_val_DeInterleaver,
		sink_sop => source_sop_ZeroRemove, source_sop => source_sop_DeInterleaver,
		sink_eop => source_eop_ZeroRemove, source_eop => source_eop_DeInterleaver
	);

u16: RSdecoderbuffer port map
	(
		clk => clock, aclr => reset,
		inputData => outputData_DeInterleaver, outputData => outputData_RSdecoderbuffer,
		sink_ena => source_ena_DeInterleaver, source_ena => source_ena_RSdecoderbuffer,
		sink_val => source_val_DeInterleaver, source_val => source_val_RSdecoderbuffer,
		sink_sop => source_sop_DeInterleaver, source_sop => source_sop_RSdecoderbuffer,
		sink_eop => source_eop_DeInterleaver, source_eop => source_eop_RSdecoderbuffer
	);

u17: RSdecoder port map
	(
		clk => clock, reset => reset,
		rsin => outputData_RSdecoderbuffer, rsout => outputData_RSdecoder,
		bypass => '0',
		sink_ena => source_ena_RSdecoderbuffer, source_ena => source_ena_RSdecoder,
		sink_val => source_val_RSdecoderbuffer, source_val => source_val_RSdecoder,
		sink_sop => source_sop_RSdecoderbuffer, source_sop => source_sop_RSdecoder,
		sink_eop => source_eop_RSdecoderbuffer, source_eop => source_eop_RSdecoder
	);

u18: Outputbuffer port map
	(
		clk => clock, aclr => reset,
		inputData => outputData_RSdecoder, outputData => outputData,
		sink_ena => source_ena_RSdecoder, source_ena => source_ena,
		sink_val => source_val_RSdecoder, source_val => source_val,
		sink_sop => source_sop_RSdecoder, source_sop => source_sop,
		sink_eop => source_eop_RSdecoder, source_eop => source_eop
	);

-- --------------------------------------------------------------------------------

end connection;

-- ================================================================================