📄 fifo_cpremovereal.vhd
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ena0 => wren_a,
ena1 => clocken1,
portaaddr => wire_ram_block2a_8portaaddr,
portadatain => wire_ram_block2a_8portadatain,
portawe => wire_ram_block2a_portawe(8),
portbaddr => wire_ram_block2a_8portbaddr,
portbdataout => wire_ram_block2a_8portbdataout,
portbrewe => wire_ram_block2a_portbrewe(8)
);
ram_block2a_9 : cyclone_ram_block
GENERIC MAP (
CONNECTIVITY_CHECKING => "OFF",
LOGICAL_RAM_NAME => "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
OPERATION_MODE => "dual_port",
PORT_A_ADDRESS_CLEAR => "none",
PORT_A_ADDRESS_WIDTH => 8,
PORT_A_DATA_IN_CLEAR => "none",
PORT_A_DATA_WIDTH => 1,
PORT_A_FIRST_ADDRESS => 0,
PORT_A_FIRST_BIT_NUMBER => 9,
PORT_A_LAST_ADDRESS => 255,
PORT_A_LOGICAL_RAM_DEPTH => 256,
PORT_A_LOGICAL_RAM_WIDTH => 10,
PORT_A_WRITE_ENABLE_CLEAR => "none",
PORT_B_ADDRESS_CLEAR => "none",
PORT_B_ADDRESS_CLOCK => "clock1",
PORT_B_ADDRESS_WIDTH => 8,
PORT_B_DATA_OUT_CLEAR => "none",
PORT_B_DATA_OUT_CLOCK => "none",
PORT_B_DATA_WIDTH => 1,
PORT_B_FIRST_ADDRESS => 0,
PORT_B_FIRST_BIT_NUMBER => 9,
PORT_B_LAST_ADDRESS => 255,
PORT_B_LOGICAL_RAM_DEPTH => 256,
PORT_B_LOGICAL_RAM_WIDTH => 10,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
RAM_BLOCK_TYPE => "auto"
)
PORT MAP (
clk0 => clock0,
clk1 => clock1,
ena0 => wren_a,
ena1 => clocken1,
portaaddr => wire_ram_block2a_9portaaddr,
portadatain => wire_ram_block2a_9portadatain,
portawe => wire_ram_block2a_portawe(9),
portbaddr => wire_ram_block2a_9portbaddr,
portbdataout => wire_ram_block2a_9portbdataout,
portbrewe => wire_ram_block2a_portbrewe(9)
);
END RTL; --fifo_CPRemoveReal_altsyncram_uia1
--synthesis_resources = M4K 20
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fifo_CPRemoveReal_dpram_g7k IS
PORT
(
data : IN STD_LOGIC_VECTOR (9 DOWNTO 0) := (OTHERS => '1');
inclock : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC := '1';
outclocken : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC
);
END fifo_CPRemoveReal_dpram_g7k;
ARCHITECTURE RTL OF fifo_CPRemoveReal_dpram_g7k IS
ATTRIBUTE synthesis_clearbox : boolean;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_altsyncram1_q_b : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT fifo_CPRemoveReal_altsyncram_uia1
PORT
(
address_a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '1');
clock0 : IN STD_LOGIC := '1';
clock1 : IN STD_LOGIC := '1';
clocken1 : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '1');
q_b : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wren_a : IN STD_LOGIC := '0'
);
END COMPONENT;
BEGIN
q <= wire_altsyncram1_q_b;
altsyncram1 : fifo_CPRemoveReal_altsyncram_uia1
PORT MAP (
address_a => wraddress,
address_b => rdaddress,
clock0 => inclock,
clock1 => outclock,
clocken1 => outclocken,
data_a => data,
q_b => wire_altsyncram1_q_b,
wren_a => wren
);
END RTL; --fifo_CPRemoveReal_dpram_g7k
--lpm_counter DEVICE_FAMILY="Cyclone" lpm_direction="UP" lpm_width=8 aclr clock cnt_en q sclr
--VERSION_BEGIN 5.1 cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_lpm_counter 2005:08:23:15:49:38:SJ cbx_lpm_decode 2005:04:27:14:28:48:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ VERSION_END
LIBRARY cyclone;
USE cyclone.all;
--synthesis_resources = lut 8
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fifo_CPRemoveReal_cntr_td8 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clock : IN STD_LOGIC;
cnt_en : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
sclr : IN STD_LOGIC := '0'
);
END fifo_CPRemoveReal_cntr_td8;
ARCHITECTURE RTL OF fifo_CPRemoveReal_cntr_td8 IS
ATTRIBUTE synthesis_clearbox : boolean;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_counter_cella_aload : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_counter_cella_0cout : STD_LOGIC;
SIGNAL wire_counter_cella_1cout : STD_LOGIC;
SIGNAL wire_counter_cella_2cout : STD_LOGIC;
SIGNAL wire_counter_cella_3cout : STD_LOGIC;
SIGNAL wire_counter_cella_4cout : STD_LOGIC;
SIGNAL wire_counter_cella_5cout : STD_LOGIC;
SIGNAL wire_counter_cella_6cout : STD_LOGIC;
SIGNAL wire_counter_cella_dataa : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_counter_cella_datac : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_counter_cella_regout : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_counter_cella_sload : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_rd_ptr_count_w_lg_w_lg_sset205w206w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_rd_ptr_count_w_lg_sset207w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_rd_ptr_count_w_lg_sset205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rd_ptr_count_w_lg_w_lg_sset207w208w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_rd_ptr_count_w_lg_sset_node209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL aclr_actual : STD_LOGIC;
SIGNAL clk_en : STD_LOGIC;
SIGNAL data : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL s_val : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL safe_q : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sload : STD_LOGIC;
SIGNAL sset : STD_LOGIC;
SIGNAL sset_node : STD_LOGIC;
COMPONENT cyclone_lcell
GENERIC
(
cin_used : STRING := "false";
lut_mask : STRING;
operation_mode : STRING := "normal";
output_mode : STRING := "reg_and_comb";
register_cascade_mode : STRING := "off";
sum_lutc_input : STRING := "datac";
synch_mode : STRING := "off";
lpm_type : STRING := "cyclone_lcell"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aload : IN STD_LOGIC := '0';
cin : IN STD_LOGIC := '0';
clk : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC := '1';
datab : IN STD_LOGIC := '1';
datac : IN STD_LOGIC := '1';
datad : IN STD_LOGIC := '1';
ena : IN STD_LOGIC := '1';
inverta : IN STD_LOGIC := '0';
regcascin : IN STD_LOGIC := '0';
regout : OUT STD_LOGIC;
sclr : IN STD_LOGIC := '0';
sload : IN STD_LOGIC := '0'
);
END COMPONENT;
BEGIN
wire_vcc <= '1';
loop21 : FOR i IN 0 TO 7 GENERATE
wire_rd_ptr_count_w_lg_w_lg_sset205w206w(i) <= wire_rd_ptr_count_w_lg_sset205w(0) AND data(i);
END GENERATE loop21;
loop22 : FOR i IN 0 TO 7 GENERATE
wire_rd_ptr_count_w_lg_sset207w(i) <= sset AND s_val(i);
END GENERATE loop22;
wire_rd_ptr_count_w_lg_sset205w(0) <= NOT sset;
loop23 : FOR i IN 0 TO 7 GENERATE
wire_rd_ptr_count_w_lg_w_lg_sset207w208w(i) <= wire_rd_ptr_count_w_lg_sset207w(i) OR wire_rd_ptr_count_w_lg_w_lg_sset205w206w(i);
END GENERATE loop23;
wire_rd_ptr_count_w_lg_sset_node209w(0) <= sset_node OR sload;
aclr_actual <= aclr;
clk_en <= '1';
data <= (OTHERS => '0');
q <= safe_q;
s_val <= "11111111";
safe_q <= wire_counter_cella_regout;
sload <= '0';
sset <= '0';
sset_node <= '0';
wire_counter_cella_aload <= "00000000";
wire_counter_cella_dataa <= safe_q;
wire_counter_cella_datac <= wire_rd_ptr_count_w_lg_w_lg_sset207w208w;
loop25 : FOR i IN 0 TO 7 GENERATE
wire_counter_cella_sload(i) <= wire_rd_ptr_count_w_lg_sset_node209w(0);
END GENERATE loop25;
counter_cella_0 : cyclone_lcell
GENERIC MAP (
cin_used => "false",
lut_mask => "66AA",
operation_mode => "arithmetic",
synch_mode => "on"
)
PORT MAP (
aclr => aclr_actual,
aload => wire_counter_cella_aload(0),
clk => clock,
cout => wire_counter_cella_0cout,
dataa => wire_counter_cella_dataa(0),
datab => cnt_en,
datac => wire_counter_cella_datac(0),
ena => clk_en,
regout => wire_counter_cella_regout(0),
sclr => sclr,
sload => wire_counter_cella_sload(0)
);
counter_cella_1 : cyclone_lcell
GENERIC MAP (
cin_used => "true",
lut_mask => "6AA0",
operation_mode => "arithmetic",
sum_lutc_input => "cin",
synch_mode => "on"
)
PORT MAP (
aclr => aclr_actual,
aload => wire_counter_cella_aload(1),
cin => wire_counter_cella_0cout,
clk => clock,
cout => wire_counter_cella_1cout,
dataa => wire_counter_cella_dataa(1),
datab => cnt_en,
datac => wire_counter_cella_datac(1),
ena => clk_en,
regout => wire_counter_cella_regout(1),
sclr => sclr,
sload => wire_counter_cella_sload(1)
);
counter_cella_2 : cyclone_lcell
GENERIC MAP (
cin_used => "true",
lut_mask => "6AA0",
operation_mode => "arithmetic",
sum_lutc_input => "cin",
synch_mode => "on"
)
PORT MAP (
aclr => aclr_actual,
aload => wire_counter_cella_aload(2),
cin => wire_counter_cella_1cout,
clk => clock,
cout => wire_counter_cella_2cout,
dataa => wire_counter_cella_dataa(2),
datab => cnt_en,
datac => wire_counter_cella_datac(2),
ena => clk_en,
regout => wire_counter_cella_regout(2),
sclr => sclr,
sload => wire_counter_cella_sload(2)
);
counter_cella_3 : cyclone_lcell
GENERIC MAP (
cin_used => "true",
lut_mask => "6AA0",
operation_mode => "arithmetic",
sum_lutc_input => "cin",
synch_mode => "on"
)
PORT MAP (
aclr => aclr_actual,
aload => wire_counter_cella_aload(3),
cin => wire_counter_cella_2cout,
clk => clock,
cout => wire_counter_cella_3cout,
dataa => wire_counter_cella_dataa(3),
datab => cnt_en,
datac => wire_counter_cella_datac(3),
ena => clk_en,
regout => wire_counter_cella_regout(3),
sclr => sclr,
sload => wire_counter_cella_sload(3)
);
counter_cella_4 : cyclone_lcell
GENERIC MAP (
cin_used => "true",
lut_mask => "6AA0",
operation_mode => "arithmetic",
sum_lutc_input => "cin",
synch_mode => "on"
)
PORT MAP (
aclr => aclr_actual,
aload => wire_counter_cella_aload(4),
cin => wire_counter_cella_3cout,
clk => clock,
cout => wire_counter_cella_4cout,
dataa => wire_counter_cella_dataa(4),
datab => cnt_en,
datac => wire_counter_cella_datac(4),
ena => clk_en,
regout => wire_counter_cella_regout(4),
sclr => sclr,
sload => wire_counter_cella_sload(4)
);
counter_cella_5 : cyclone_lcell
GENERIC MAP (
cin_used => "true",
lut_mask => "6AA0",
operation_mode => "arithmetic",
sum_lutc_input => "cin",
synch_mode => "on"
)
PORT MAP (
aclr => aclr_actual,
aload => wire_counter_cella_aload(5),
cin => wire_counter_cella_4cout,
clk => clock,
cout => wire_counter_cella_5cout,
dataa => wire_counter_cella_dataa(5),
datab => cnt_en,
datac => wire_counter_cella_datac(5),
ena => clk_en,
regout => wire_counter_cella_regout(5),
sclr => sclr,
sload => wire_counter_cella_sload(5)
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