ram_cpremoveimag.vhd

RS的编码。最新的移动多媒体应用技术的源代码

		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		POWER_UP_UNINITIALIZED => "false",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock0,
		clr0 => aclr0,
		ena0 => wren_a,
		portaaddr => wire_ram_block1a_7portaaddr,
		portadatain => wire_ram_block1a_7portadatain,
		portawe => wire_ram_block1a_portawe(7),
		portbaddr => wire_ram_block1a_7portbaddr,
		portbdataout => wire_ram_block1a_7portbdataout,
		portbrewe => rden_b
	  );
	ram_block1a_8 :  cyclone_ram_block
	  GENERIC MAP (
		CONNECTIVITY_CHECKING => "OFF",
		LOGICAL_RAM_NAME => "ALTSYNCRAM",
		MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
		OPERATION_MODE => "dual_port",
		PORT_A_ADDRESS_CLEAR => "clear0",
		PORT_A_ADDRESS_WIDTH => 7,
		PORT_A_DATA_IN_CLEAR => "clear0",
		PORT_A_DATA_WIDTH => 1,
		PORT_A_FIRST_ADDRESS => 0,
		PORT_A_FIRST_BIT_NUMBER => 8,
		PORT_A_LAST_ADDRESS => 79,
		PORT_A_LOGICAL_RAM_DEPTH => 80,
		PORT_A_LOGICAL_RAM_WIDTH => 10,
		PORT_A_WRITE_ENABLE_CLEAR => "clear0",
		PORT_B_ADDRESS_CLEAR => "clear0",
		PORT_B_ADDRESS_CLOCK => "clock1",
		PORT_B_ADDRESS_WIDTH => 7,
		PORT_B_DATA_OUT_CLEAR => "clear0",
		PORT_B_DATA_OUT_CLOCK => "clock1",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 8,
		PORT_B_LAST_ADDRESS => 79,
		PORT_B_LOGICAL_RAM_DEPTH => 80,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR => "clear0",
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		POWER_UP_UNINITIALIZED => "false",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock0,
		clr0 => aclr0,
		ena0 => wren_a,
		portaaddr => wire_ram_block1a_8portaaddr,
		portadatain => wire_ram_block1a_8portadatain,
		portawe => wire_ram_block1a_portawe(8),
		portbaddr => wire_ram_block1a_8portbaddr,
		portbdataout => wire_ram_block1a_8portbdataout,
		portbrewe => rden_b
	  );
	ram_block1a_9 :  cyclone_ram_block
	  GENERIC MAP (
		CONNECTIVITY_CHECKING => "OFF",
		LOGICAL_RAM_NAME => "ALTSYNCRAM",
		MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
		OPERATION_MODE => "dual_port",
		PORT_A_ADDRESS_CLEAR => "clear0",
		PORT_A_ADDRESS_WIDTH => 7,
		PORT_A_DATA_IN_CLEAR => "clear0",
		PORT_A_DATA_WIDTH => 1,
		PORT_A_FIRST_ADDRESS => 0,
		PORT_A_FIRST_BIT_NUMBER => 9,
		PORT_A_LAST_ADDRESS => 79,
		PORT_A_LOGICAL_RAM_DEPTH => 80,
		PORT_A_LOGICAL_RAM_WIDTH => 10,
		PORT_A_WRITE_ENABLE_CLEAR => "clear0",
		PORT_B_ADDRESS_CLEAR => "clear0",
		PORT_B_ADDRESS_CLOCK => "clock1",
		PORT_B_ADDRESS_WIDTH => 7,
		PORT_B_DATA_OUT_CLEAR => "clear0",
		PORT_B_DATA_OUT_CLOCK => "clock1",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 9,
		PORT_B_LAST_ADDRESS => 79,
		PORT_B_LOGICAL_RAM_DEPTH => 80,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR => "clear0",
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		POWER_UP_UNINITIALIZED => "false",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock0,
		clr0 => aclr0,
		ena0 => wren_a,
		portaaddr => wire_ram_block1a_9portaaddr,
		portadatain => wire_ram_block1a_9portadatain,
		portawe => wire_ram_block1a_portawe(9),
		portbaddr => wire_ram_block1a_9portbaddr,
		portbdataout => wire_ram_block1a_9portbdataout,
		portbrewe => rden_b
	  );

 END RTL; --ram_CPremoveImag_altsyncram_57e1
--VALID FILE


LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY ram_CPremoveImag IS
	PORT
	(
		aclr		: IN STD_LOGIC  := '0';
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		rden		: IN STD_LOGIC  := '1';
		wraddress		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		q		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END ram_CPremoveImag;


ARCHITECTURE RTL OF ram_cpremoveimag IS

	ATTRIBUTE synthesis_clearbox: boolean;
	ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (9 DOWNTO 0);



	COMPONENT ram_CPremoveImag_altsyncram_57e1
	PORT (
			wren_a	: IN STD_LOGIC ;
			aclr0	: IN STD_LOGIC ;
			clock0	: IN STD_LOGIC ;
			address_a	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
			address_b	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
			rden_b	: IN STD_LOGIC ;
			q_b	: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
			data_a	: IN STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
	END COMPONENT;

BEGIN
	q    <= sub_wire0(9 DOWNTO 0);

	ram_CPremoveImag_altsyncram_57e1_component : ram_CPremoveImag_altsyncram_57e1
	PORT MAP (
		wren_a => wren,
		aclr0 => aclr,
		clock0 => clock,
		address_a => wraddress,
		address_b => rdaddress,
		rden_b => rden,
		data_a => data,
		q_b => sub_wire0
	);



END RTL;

-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "1"
-- Retrieval info: PRIVATE: CLRq NUMERIC "1"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "1"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "1"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "800"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "10"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "10"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "10"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "10"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "1"
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "CLEAR0"
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "CLEAR0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INDATA_ACLR_A STRING "CLEAR0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "80"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "80"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: RDCONTROL_ACLR_B STRING "CLEAR0"
-- Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "CLEAR0"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL data[9..0]
-- Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL q[9..0]
-- Retrieval info: USED_PORT: rdaddress 0 0 7 0 INPUT NODEFVAL rdaddress[6..0]
-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC rden
-- Retrieval info: USED_PORT: wraddress 0 0 7 0 INPUT NODEFVAL wraddress[6..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
-- Retrieval info: CONNECT: @data_a 0 0 10 0 data 0 0 10 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 10 0 @q_b 0 0 10 0
-- Retrieval info: CONNECT: @address_a 0 0 7 0 wraddress 0 0 7 0
-- Retrieval info: CONNECT: @address_b 0 0 7 0 rdaddress 0 0 7 0
-- Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_CPremoveImag.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_CPremoveImag.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_CPremoveImag.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_CPremoveImag.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_CPremoveImag_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_CPremoveImag_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_CPremoveImag_wave*.jpg FALSE