fifo_cpremove.vhd

RS的编码。最新的移动多媒体应用技术的源代码

	  );
	counter_cella_6 :  cyclone_lcell
	  GENERIC MAP (
		cin_used => "true",
		lut_mask => "6AA0",
		operation_mode => "arithmetic",
		sum_lutc_input => "cin",
		synch_mode => "on"
	  )
	  PORT MAP ( 
		aclr => aclr_actual,
		aload => wire_counter_cella_aload(6),
		cin => wire_counter_cella_5cout,
		clk => clock,
		cout => wire_counter_cella_6cout,
		dataa => wire_counter_cella_dataa(6),
		datab => cnt_en,
		datac => wire_counter_cella_datac(6),
		ena => clk_en,
		regout => wire_counter_cella_regout(6),
		sclr => sclr,
		sload => wire_counter_cella_sload(6)
	  );
	counter_cella_7 :  cyclone_lcell
	  GENERIC MAP (
		cin_used => "true",
		lut_mask => "6AA0",
		operation_mode => "normal",
		sum_lutc_input => "cin",
		synch_mode => "on"
	  )
	  PORT MAP ( 
		aclr => aclr_actual,
		aload => wire_counter_cella_aload(7),
		cin => wire_counter_cella_6cout,
		clk => clock,
		dataa => wire_counter_cella_dataa(7),
		datab => cnt_en,
		datac => wire_counter_cella_datac(7),
		datad => wire_vcc,
		ena => clk_en,
		regout => wire_counter_cella_regout(7),
		sclr => sclr,
		sload => wire_counter_cella_sload(7)
	  );

 END RTL; --fifo_CPRemove_cntr_td8

--synthesis_resources = lut 18 M4K 20 
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;

 ENTITY  fifo_CPRemove_a_dpfifo_sfm IS 
	 PORT 
	 ( 
		 aclr	:	IN  STD_LOGIC := '0';
		 clock	:	IN  STD_LOGIC;
		 data	:	IN  STD_LOGIC_VECTOR (9 DOWNTO 0);
		 q	:	OUT  STD_LOGIC_VECTOR (9 DOWNTO 0);
		 rreq	:	IN  STD_LOGIC;
		 sclr	:	IN  STD_LOGIC := '0';
		 usedw	:	OUT  STD_LOGIC_VECTOR (7 DOWNTO 0);
		 wreq	:	IN  STD_LOGIC
	 ); 
 END fifo_CPRemove_a_dpfifo_sfm;

 ARCHITECTURE RTL OF fifo_CPRemove_a_dpfifo_sfm IS

	 ATTRIBUTE synthesis_clearbox : boolean;
	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
	 SIGNAL  wire_fifo_state_usedw_out	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_FIFOram_outclocken	:	STD_LOGIC;
	 SIGNAL  wire_dpfifo_w_lg_valid_rreq3w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_FIFOram_q	:	STD_LOGIC_VECTOR (9 DOWNTO 0);
	 SIGNAL  wire_FIFOram_rdaddress	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_rd_ptr_count_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_wr_ptr_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_dpfifo_w_lg_w_lg_sclr1w2w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_dpfifo_w_lg_sclr1w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  rd_ptr :	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  valid_rreq :	STD_LOGIC;
	 SIGNAL  valid_wreq :	STD_LOGIC;
	 COMPONENT  fifo_CPRemove_a_fefifo_qce
	 PORT
	 ( 
		aclr	:	IN  STD_LOGIC := '0';
		clock	:	IN  STD_LOGIC;
		rreq	:	IN  STD_LOGIC := '0';
		sclr	:	IN  STD_LOGIC := '0';
		usedw_out	:	OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
		wreq	:	IN  STD_LOGIC := '0'
	 ); 
	 END COMPONENT;
	 COMPONENT  fifo_CPRemove_dpram_g7k
	 PORT
	 ( 
		data	:	IN  STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '1');
		inclock	:	IN  STD_LOGIC := '1';
		outclock	:	IN  STD_LOGIC := '1';
		outclocken	:	IN  STD_LOGIC := '1';
		q	:	OUT  STD_LOGIC_VECTOR(9 DOWNTO 0);
		rdaddress	:	IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
		wraddress	:	IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
		wren	:	IN  STD_LOGIC
	 ); 
	 END COMPONENT;
	 COMPONENT  fifo_CPRemove_cntr_td8
	 PORT
	 ( 
		aclr	:	IN  STD_LOGIC := '0';
		clock	:	IN  STD_LOGIC;
		cnt_en	:	IN  STD_LOGIC := '1';
		q	:	OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
		sclr	:	IN  STD_LOGIC := '0'
	 ); 
	 END COMPONENT;
 BEGIN

	loop26 : FOR i IN 0 TO 7 GENERATE 
		wire_dpfifo_w_lg_w_lg_sclr1w2w(i) <= wire_dpfifo_w_lg_sclr1w(0) AND rd_ptr(i);
	END GENERATE loop26;
	wire_dpfifo_w_lg_sclr1w(0) <= NOT sclr;
	q <= wire_FIFOram_q;
	rd_ptr <= wire_rd_ptr_count_q;
	usedw <= wire_fifo_state_usedw_out;
	valid_rreq <= rreq;
	valid_wreq <= wreq;
	fifo_state :  fifo_CPRemove_a_fefifo_qce
	  PORT MAP ( 
		aclr => aclr,
		clock => clock,
		rreq => rreq,
		sclr => sclr,
		usedw_out => wire_fifo_state_usedw_out,
		wreq => wreq
	  );
	wire_FIFOram_outclocken <= wire_dpfifo_w_lg_valid_rreq3w(0);
	wire_dpfifo_w_lg_valid_rreq3w(0) <= valid_rreq OR sclr;
	wire_FIFOram_rdaddress <= wire_dpfifo_w_lg_w_lg_sclr1w2w;
	FIFOram :  fifo_CPRemove_dpram_g7k
	  PORT MAP ( 
		data => data,
		inclock => clock,
		outclock => clock,
		outclocken => wire_FIFOram_outclocken,
		q => wire_FIFOram_q,
		rdaddress => wire_FIFOram_rdaddress,
		wraddress => wire_wr_ptr_q,
		wren => valid_wreq
	  );
	rd_ptr_count :  fifo_CPRemove_cntr_td8
	  PORT MAP ( 
		aclr => aclr,
		clock => clock,
		cnt_en => valid_rreq,
		q => wire_rd_ptr_count_q,
		sclr => sclr
	  );
	wr_ptr :  fifo_CPRemove_cntr_td8
	  PORT MAP ( 
		aclr => aclr,
		clock => clock,
		cnt_en => valid_wreq,
		q => wire_wr_ptr_q,
		sclr => sclr
	  );

 END RTL; --fifo_CPRemove_a_dpfifo_sfm

--synthesis_resources = lut 18 M4K 20 
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;

 ENTITY  fifo_CPRemove_scfifo_s8k IS 
	 PORT 
	 ( 
		 aclr	:	IN  STD_LOGIC := '0';
		 clock	:	IN  STD_LOGIC;
		 data	:	IN  STD_LOGIC_VECTOR (9 DOWNTO 0);
		 q	:	OUT  STD_LOGIC_VECTOR (9 DOWNTO 0);
		 rdreq	:	IN  STD_LOGIC;
		 usedw	:	OUT  STD_LOGIC_VECTOR (7 DOWNTO 0);
		 wrreq	:	IN  STD_LOGIC
	 ); 
 END fifo_CPRemove_scfifo_s8k;

 ARCHITECTURE RTL OF fifo_CPRemove_scfifo_s8k IS

	 ATTRIBUTE synthesis_clearbox : boolean;
	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
	 SIGNAL  wire_dpfifo_q	:	STD_LOGIC_VECTOR (9 DOWNTO 0);
	 SIGNAL  wire_dpfifo_usedw	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  sclr	:	STD_LOGIC;
	 COMPONENT  fifo_CPRemove_a_dpfifo_sfm
	 PORT
	 ( 
		aclr	:	IN  STD_LOGIC := '0';
		clock	:	IN  STD_LOGIC;
		data	:	IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
		q	:	OUT  STD_LOGIC_VECTOR(9 DOWNTO 0);
		rreq	:	IN  STD_LOGIC;
		sclr	:	IN  STD_LOGIC := '0';
		usedw	:	OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
		wreq	:	IN  STD_LOGIC
	 ); 
	 END COMPONENT;
 BEGIN

	q <= wire_dpfifo_q;
	sclr <= '0';
	usedw <= wire_dpfifo_usedw;
	dpfifo :  fifo_CPRemove_a_dpfifo_sfm
	  PORT MAP ( 
		aclr => aclr,
		clock => clock,
		data => data,
		q => wire_dpfifo_q,
		rreq => rdreq,
		sclr => sclr,
		usedw => wire_dpfifo_usedw,
		wreq => wrreq
	  );

 END RTL; --fifo_CPRemove_scfifo_s8k
--VALID FILE


LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY fifo_CPRemove IS
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		rdreq		: IN STD_LOGIC ;
		wrreq		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
		usedw		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END fifo_CPRemove;


ARCHITECTURE RTL OF fifo_cpremove IS

	ATTRIBUTE synthesis_clearbox: boolean;
	ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (9 DOWNTO 0);



	COMPONENT fifo_CPRemove_scfifo_s8k
	PORT (
			usedw	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			rdreq	: IN STD_LOGIC ;
			aclr	: IN STD_LOGIC ;
			clock	: IN STD_LOGIC ;
			q	: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
			wrreq	: IN STD_LOGIC ;
			data	: IN STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
	END COMPONENT;

BEGIN
	usedw    <= sub_wire0(7 DOWNTO 0);
	q    <= sub_wire1(9 DOWNTO 0);

	fifo_CPRemove_scfifo_s8k_component : fifo_CPRemove_scfifo_s8k
	PORT MAP (
		rdreq => rdreq,
		aclr => aclr,
		clock => clock,
		wrreq => wrreq,
		data => data,
		usedw => sub_wire0,
		q => sub_wire1
	);



END RTL;

-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "256"
-- Retrieval info: PRIVATE: Empty NUMERIC "0"
-- Retrieval info: PRIVATE: Full NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "10"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL data[9..0]
-- Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL q[9..0]
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-- Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-- Retrieval info: CONNECT: @data 0 0 10 0 data 0 0 10 0
-- Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_CPRemove.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_CPRemove.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_CPRemove.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_CPRemove.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_CPRemove_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_CPRemove_waveforms.html TRUE
-- Retrieval i