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📄 fifo_cpremove.vhd

📁 RS的编码。最新的移动多媒体应用技术的源代码
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		PORT_B_DATA_OUT_CLOCK => "none",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 0,
		PORT_B_LAST_ADDRESS => 255,
		PORT_B_LOGICAL_RAM_DEPTH => 256,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock1,
		ena0 => wren_a,
		ena1 => clocken1,
		portaaddr => wire_ram_block2a_0portaaddr,
		portadatain => wire_ram_block2a_0portadatain,
		portawe => wire_ram_block2a_portawe(0),
		portbaddr => wire_ram_block2a_0portbaddr,
		portbdataout => wire_ram_block2a_0portbdataout,
		portbrewe => wire_ram_block2a_portbrewe(0)
	  );
	ram_block2a_1 :  cyclone_ram_block
	  GENERIC MAP (
		CONNECTIVITY_CHECKING => "OFF",
		LOGICAL_RAM_NAME => "ALTSYNCRAM",
		MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
		OPERATION_MODE => "dual_port",
		PORT_A_ADDRESS_CLEAR => "none",
		PORT_A_ADDRESS_WIDTH => 8,
		PORT_A_DATA_IN_CLEAR => "none",
		PORT_A_DATA_WIDTH => 1,
		PORT_A_FIRST_ADDRESS => 0,
		PORT_A_FIRST_BIT_NUMBER => 1,
		PORT_A_LAST_ADDRESS => 255,
		PORT_A_LOGICAL_RAM_DEPTH => 256,
		PORT_A_LOGICAL_RAM_WIDTH => 10,
		PORT_A_WRITE_ENABLE_CLEAR => "none",
		PORT_B_ADDRESS_CLEAR => "none",
		PORT_B_ADDRESS_CLOCK => "clock1",
		PORT_B_ADDRESS_WIDTH => 8,
		PORT_B_DATA_OUT_CLEAR => "none",
		PORT_B_DATA_OUT_CLOCK => "none",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 1,
		PORT_B_LAST_ADDRESS => 255,
		PORT_B_LOGICAL_RAM_DEPTH => 256,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock1,
		ena0 => wren_a,
		ena1 => clocken1,
		portaaddr => wire_ram_block2a_1portaaddr,
		portadatain => wire_ram_block2a_1portadatain,
		portawe => wire_ram_block2a_portawe(1),
		portbaddr => wire_ram_block2a_1portbaddr,
		portbdataout => wire_ram_block2a_1portbdataout,
		portbrewe => wire_ram_block2a_portbrewe(1)
	  );
	ram_block2a_2 :  cyclone_ram_block
	  GENERIC MAP (
		CONNECTIVITY_CHECKING => "OFF",
		LOGICAL_RAM_NAME => "ALTSYNCRAM",
		MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
		OPERATION_MODE => "dual_port",
		PORT_A_ADDRESS_CLEAR => "none",
		PORT_A_ADDRESS_WIDTH => 8,
		PORT_A_DATA_IN_CLEAR => "none",
		PORT_A_DATA_WIDTH => 1,
		PORT_A_FIRST_ADDRESS => 0,
		PORT_A_FIRST_BIT_NUMBER => 2,
		PORT_A_LAST_ADDRESS => 255,
		PORT_A_LOGICAL_RAM_DEPTH => 256,
		PORT_A_LOGICAL_RAM_WIDTH => 10,
		PORT_A_WRITE_ENABLE_CLEAR => "none",
		PORT_B_ADDRESS_CLEAR => "none",
		PORT_B_ADDRESS_CLOCK => "clock1",
		PORT_B_ADDRESS_WIDTH => 8,
		PORT_B_DATA_OUT_CLEAR => "none",
		PORT_B_DATA_OUT_CLOCK => "none",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 2,
		PORT_B_LAST_ADDRESS => 255,
		PORT_B_LOGICAL_RAM_DEPTH => 256,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock1,
		ena0 => wren_a,
		ena1 => clocken1,
		portaaddr => wire_ram_block2a_2portaaddr,
		portadatain => wire_ram_block2a_2portadatain,
		portawe => wire_ram_block2a_portawe(2),
		portbaddr => wire_ram_block2a_2portbaddr,
		portbdataout => wire_ram_block2a_2portbdataout,
		portbrewe => wire_ram_block2a_portbrewe(2)
	  );
	ram_block2a_3 :  cyclone_ram_block
	  GENERIC MAP (
		CONNECTIVITY_CHECKING => "OFF",
		LOGICAL_RAM_NAME => "ALTSYNCRAM",
		MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
		OPERATION_MODE => "dual_port",
		PORT_A_ADDRESS_CLEAR => "none",
		PORT_A_ADDRESS_WIDTH => 8,
		PORT_A_DATA_IN_CLEAR => "none",
		PORT_A_DATA_WIDTH => 1,
		PORT_A_FIRST_ADDRESS => 0,
		PORT_A_FIRST_BIT_NUMBER => 3,
		PORT_A_LAST_ADDRESS => 255,
		PORT_A_LOGICAL_RAM_DEPTH => 256,
		PORT_A_LOGICAL_RAM_WIDTH => 10,
		PORT_A_WRITE_ENABLE_CLEAR => "none",
		PORT_B_ADDRESS_CLEAR => "none",
		PORT_B_ADDRESS_CLOCK => "clock1",
		PORT_B_ADDRESS_WIDTH => 8,
		PORT_B_DATA_OUT_CLEAR => "none",
		PORT_B_DATA_OUT_CLOCK => "none",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 3,
		PORT_B_LAST_ADDRESS => 255,
		PORT_B_LOGICAL_RAM_DEPTH => 256,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock1,
		ena0 => wren_a,
		ena1 => clocken1,
		portaaddr => wire_ram_block2a_3portaaddr,
		portadatain => wire_ram_block2a_3portadatain,
		portawe => wire_ram_block2a_portawe(3),
		portbaddr => wire_ram_block2a_3portbaddr,
		portbdataout => wire_ram_block2a_3portbdataout,
		portbrewe => wire_ram_block2a_portbrewe(3)
	  );
	ram_block2a_4 :  cyclone_ram_block
	  GENERIC MAP (
		CONNECTIVITY_CHECKING => "OFF",
		LOGICAL_RAM_NAME => "ALTSYNCRAM",
		MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
		OPERATION_MODE => "dual_port",
		PORT_A_ADDRESS_CLEAR => "none",
		PORT_A_ADDRESS_WIDTH => 8,
		PORT_A_DATA_IN_CLEAR => "none",
		PORT_A_DATA_WIDTH => 1,
		PORT_A_FIRST_ADDRESS => 0,
		PORT_A_FIRST_BIT_NUMBER => 4,
		PORT_A_LAST_ADDRESS => 255,
		PORT_A_LOGICAL_RAM_DEPTH => 256,
		PORT_A_LOGICAL_RAM_WIDTH => 10,
		PORT_A_WRITE_ENABLE_CLEAR => "none",
		PORT_B_ADDRESS_CLEAR => "none",
		PORT_B_ADDRESS_CLOCK => "clock1",
		PORT_B_ADDRESS_WIDTH => 8,
		PORT_B_DATA_OUT_CLEAR => "none",
		PORT_B_DATA_OUT_CLOCK => "none",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 4,
		PORT_B_LAST_ADDRESS => 255,
		PORT_B_LOGICAL_RAM_DEPTH => 256,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock1,
		ena0 => wren_a,
		ena1 => clocken1,
		portaaddr => wire_ram_block2a_4portaaddr,
		portadatain => wire_ram_block2a_4portadatain,
		portawe => wire_ram_block2a_portawe(4),
		portbaddr => wire_ram_block2a_4portbaddr,
		portbdataout => wire_ram_block2a_4portbdataout,
		portbrewe => wire_ram_block2a_portbrewe(4)
	  );
	ram_block2a_5 :  cyclone_ram_block
	  GENERIC MAP (
		CONNECTIVITY_CHECKING => "OFF",
		LOGICAL_RAM_NAME => "ALTSYNCRAM",
		MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
		OPERATION_MODE => "dual_port",
		PORT_A_ADDRESS_CLEAR => "none",
		PORT_A_ADDRESS_WIDTH => 8,
		PORT_A_DATA_IN_CLEAR => "none",
		PORT_A_DATA_WIDTH => 1,
		PORT_A_FIRST_ADDRESS => 0,
		PORT_A_FIRST_BIT_NUMBER => 5,
		PORT_A_LAST_ADDRESS => 255,
		PORT_A_LOGICAL_RAM_DEPTH => 256,
		PORT_A_LOGICAL_RAM_WIDTH => 10,
		PORT_A_WRITE_ENABLE_CLEAR => "none",
		PORT_B_ADDRESS_CLEAR => "none",
		PORT_B_ADDRESS_CLOCK => "clock1",
		PORT_B_ADDRESS_WIDTH => 8,
		PORT_B_DATA_OUT_CLEAR => "none",
		PORT_B_DATA_OUT_CLOCK => "none",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 5,
		PORT_B_LAST_ADDRESS => 255,
		PORT_B_LOGICAL_RAM_DEPTH => 256,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock1,
		ena0 => wren_a,
		ena1 => clocken1,
		portaaddr => wire_ram_block2a_5portaaddr,
		portadatain => wire_ram_block2a_5portadatain,
		portawe => wire_ram_block2a_portawe(5),
		portbaddr => wire_ram_block2a_5portbaddr,
		portbdataout => wire_ram_block2a_5portbdataout,
		portbrewe => wire_ram_block2a_portbrewe(5)
	  );
	ram_block2a_6 :  cyclone_ram_block
	  GENERIC MAP (
		CONNECTIVITY_CHECKING => "OFF",
		LOGICAL_RAM_NAME => "ALTSYNCRAM",
		MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
		OPERATION_MODE => "dual_port",
		PORT_A_ADDRESS_CLEAR => "none",
		PORT_A_ADDRESS_WIDTH => 8,
		PORT_A_DATA_IN_CLEAR => "none",
		PORT_A_DATA_WIDTH => 1,
		PORT_A_FIRST_ADDRESS => 0,
		PORT_A_FIRST_BIT_NUMBER => 6,
		PORT_A_LAST_ADDRESS => 255,
		PORT_A_LOGICAL_RAM_DEPTH => 256,
		PORT_A_LOGICAL_RAM_WIDTH => 10,
		PORT_A_WRITE_ENABLE_CLEAR => "none",
		PORT_B_ADDRESS_CLEAR => "none",
		PORT_B_ADDRESS_CLOCK => "clock1",
		PORT_B_ADDRESS_WIDTH => 8,
		PORT_B_DATA_OUT_CLEAR => "none",
		PORT_B_DATA_OUT_CLOCK => "none",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 6,
		PORT_B_LAST_ADDRESS => 255,
		PORT_B_LOGICAL_RAM_DEPTH => 256,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock1,
		ena0 => wren_a,
		ena1 => clocken1,
		portaaddr => wire_ram_block2a_6portaaddr,
		portadatain => wire_ram_block2a_6portadatain,
		portawe => wire_ram_block2a_portawe(6),
		portbaddr => wire_ram_block2a_6portbaddr,
		portbdataout => wire_ram_block2a_6portbdataout,
		portbrewe => wire_ram_block2a_portbrewe(6)
	  );
	ram_block2a_7 :  cyclone_ram_block
	  GENERIC MAP (
		CONNECTIVITY_CHECKING => "OFF",
		LOGICAL_RAM_NAME => "ALTSYNCRAM",
		MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
		OPERATION_MODE => "dual_port",
		PORT_A_ADDRESS_CLEAR => "none",
		PORT_A_ADDRESS_WIDTH => 8,
		PORT_A_DATA_IN_CLEAR => "none",
		PORT_A_DATA_WIDTH => 1,
		PORT_A_FIRST_ADDRESS => 0,
		PORT_A_FIRST_BIT_NUMBER => 7,
		PORT_A_LAST_ADDRESS => 255,
		PORT_A_LOGICAL_RAM_DEPTH => 256,
		PORT_A_LOGICAL_RAM_WIDTH => 10,
		PORT_A_WRITE_ENABLE_CLEAR => "none",
		PORT_B_ADDRESS_CLEAR => "none",
		PORT_B_ADDRESS_CLOCK => "clock1",
		PORT_B_ADDRESS_WIDTH => 8,
		PORT_B_DATA_OUT_CLEAR => "none",
		PORT_B_DATA_OUT_CLOCK => "none",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 7,
		PORT_B_LAST_ADDRESS => 255,
		PORT_B_LOGICAL_RAM_DEPTH => 256,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock1,
		ena0 => wren_a,
		ena1 => clocken1,
		portaaddr => wire_ram_block2a_7portaaddr,
		portadatain => wire_ram_block2a_7portadatain,
		portawe => wire_ram_block2a_portawe(7),
		portbaddr => wire_ram_block2a_7portbaddr,
		portbdataout => wire_ram_block2a_7portbdataout,
		portbrewe => wire_ram_block2a_portbrewe(7)
	  );
	ram_block2a_8 :  cyclone_ram_block
	  GENERIC MAP (
		CONNECTIVITY_CHECKING => "OFF",
		LOGICAL_RAM_NAME => "ALTSYNCRAM",
		MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
		OPERATION_MODE => "dual_port",
		PORT_A_ADDRESS_CLEAR => "none",
		PORT_A_ADDRESS_WIDTH => 8,
		PORT_A_DATA_IN_CLEAR => "none",
		PORT_A_DATA_WIDTH => 1,
		PORT_A_FIRST_ADDRESS => 0,
		PORT_A_FIRST_BIT_NUMBER => 8,
		PORT_A_LAST_ADDRESS => 255,
		PORT_A_LOGICAL_RAM_DEPTH => 256,
		PORT_A_LOGICAL_RAM_WIDTH => 10,
		PORT_A_WRITE_ENABLE_CLEAR => "none",
		PORT_B_ADDRESS_CLEAR => "none",
		PORT_B_ADDRESS_CLOCK => "clock1",
		PORT_B_ADDRESS_WIDTH => 8,
		PORT_B_DATA_OUT_CLEAR => "none",
		PORT_B_DATA_OUT_CLOCK => "none",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 8,
		PORT_B_LAST_ADDRESS => 255,
		PORT_B_LOGICAL_RAM_DEPTH => 256,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock1,
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