right.vhd

来自「right.vhd 序列发生器 s_machine.vhd 序列检测器 波形」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE ieee.std_logic_1164.all;
ENTITY right IS
PORT(clkr,wr:IN	 std_logic;
	  CO	:OUT std_logic
 	 );
END right;

ARCHITECTURE r OF right IS
	BEGIN
		PROCESS(clkr,wr)
		CONSTANT SERIALY :std_logic_vector(0 to 6):="0100111";
		CONSTANT SERIALN :std_logic_vector(0 to 6):="1100111";
		VARIABLE count:integer range 0 to 6 :=0; 
		BEGIN
			IF clkr = '1' AND clkr'EVENT THEN
				IF(count > 5)THEN count := 0;
				ELSE count:= count+1;
				END IF;
			END IF;
			IF(wr = '1')THEN
				CO<= SERIALY(count);
			ELSE 
				CO<=SERIALN(count);
			END IF;
		END PROCESS;
END r;