count16.vhd

来自「count16.vhd 16位BCD计数器VHDL源程序」· VHDL 代码 · 共 42 行

LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY count16 IS
	PORT
	(
		en : IN std_logic;					
		clear : IN std_logic;
   		clk : IN std_logic;
        cout : OUT std_logic;--进位
		qh : BUFFER std_logic_vector(3 downto 0);--计数高位
		ql : BUFFER std_logic_vector(3 downto 0) --此处不能有分号，计数低位
	);
END count16;

ARCHITECTURE behave OF count16 IS
BEGIN
	cout<='1' WHEN(qh="0001" and ql="0101" and en='1')ELSE '0';--计数到14时，进位位输出1
 	PROCESS (clk,clear)
		BEGIN
			IF(clear='0') THEN--复位
				qh<="0000";
				ql<="0000";
			ELSIF(clk'event and clk='1') THEN
				IF(en='1')THEN
					 IF(qh=1 and ql>4)THEN--计满15返0
						qh<="0000";
						ql<="0000";
					 ELSE
						IF(qh<1 and ql=9)THEN
							ql<="0000";
					    	qh<=qh+1;
				 	    ELSE
							ql<=ql+1;
					    END IF;
					 END IF;
			     END IF;
			 END IF;
	END PROCESS;
END behave;