multi4.vhd

fulladder.vhd 一位全加器 adder.vhd 四位全加器 multi4.vhd 四位并行乘法器

LIBRARY IEEE;
USE ieee.std_logic_1164.all;
ENTITY multi4 IS
	PORT(XA0,XA1,XA2,XA3,XB0,XB1,XB2,XB3: IN std_logic;
		 P0,P1,P2,P3,P4,P5,P6,P7: OUT std_logic
		);
END ENTITY;

ARCHITECTURE multi of multi4 IS
	COMPONENT adder
		PORT(A0,A1,A2,A3,B0,B1,B2,B3,CI: IN std_logic;
	 		 S0,S1,S2,S3,CO: OUT std_logic
 	 		 );	
    END COMPONENT;
	SIGNAL XB01,XB02,XB03,XB11,XB12,XB13,XB14,XB21,XB22,XB23,XB24,XB31,
		   XB32,XB33,XB34,U11,U12,U13,CI1,U21,U22,U23,CI2,GND: std_logic;
	BEGIN
			GND<='0';
-----------XB0------------------
			P0<=XA0 and XB0;
			XB01<=XA1 and XB0;
			XB02<=XA2 and XB0;
			XB03<=XA3 and XB0;

------------XB1-------------------
			XB11<=XA0 and XB1;
			XB12<=XA1 and XB1;
			XB13<=XA2 and XB1;
			XB14<=XA3 and XB1;

		U1:adder PORT MAP(A0=>XB01,A1=>XB02,A2=>XB03,A3=>GND,CI=>GND,
						  B0=>XB11,B1=>XB12,B2=>XB13,B3=>XB14,
						  S0=>P1,S1=>U11,S2=>U12,S3=>U13,CO=>CI1);
------------XB2--------------------
			XB21<=XA0 and XB2;
			XB22<=XA1 and XB2;
			XB23<=XA2 and XB2;
			XB24<=XA3 and XB2;


		U2:adder PORT MAP(A0=>U11,A1=>U12,A2=>U13,A3=>CI1,CI=>GND,
						  B0=>XB21,B1=>XB22,B2=>XB23,B3=>XB24,
						  S0=>P2,S1=>U21,S2=>U22,S3=>U23,CO=>CI2);

--------------XB3------------------------
			XB31<=XA0 and XB3;
			XB32<=XA1 and XB3;
			XB33<=XA2 and XB3;
			XB34<=XA3 and XB3;


		U3:adder PORT MAP(A0=>U21,A1=>U22,A2=>U23,A3=>CI2,CI=>GND,
						  B0=>XB31,B1=>XB32,B2=>XB33,B3=>XB34,
						  S0=>P3,S1=>P4,S2=>P5,S3=>P6,CO=>P7);
end multi;