adder.vhd

来自「fulladder.vhd 一位全加器 adder.vhd 四位全加器 mu」· VHDL 代码 · 共 21 行

LIBRARY IEEE;
USE ieee.std_logic_1164.all;
ENTITY adder IS
PORT(A0,A1,A2,A3,B0,B1,B2,B3,CI: IN std_logic;
	 S0,S1,S2,S3,CO: OUT std_logic
 	 );
END adder;

ARCHITECTURE ad4 OF adder IS
	COMPONENT fulladder
		PORT(a,b,c: in std_logic;
	  		 sum,carry: out std_logic);
	END COMPONENT;
	SIGNAL C0,C1,C2: std_logic;
	BEGIN
		u1:fulladder PORT MAP(c=>CI,a=>A0,b=>B0,sum=>S0,carry=>C0);
		u2:fulladder PORT MAP(c=>C0,a=>A1,b=>B1,sum=>S1,carry=>C1);
		u3:fulladder PORT MAP(c=>C1,a=>A2,b=>B2,sum=>S2,carry=>C2);
		u4:fulladder PORT MAP(c=>C2,a=>A3,b=>B3,sum=>S3,carry=>CO);
	END ad4;