fulladder.vhd

来自「fulladder.vhd 一位全加器 adder.vhd 四位全加器 mu」· VHDL 代码 · 共 13 行

LIBRARY IEEE;
USE ieee.std_logic_1164.all;
entity fulladder is
port (a,b,c: in std_logic;
	  sum,carry: out std_logic);
end fulladder;

architecture concurrent of fulladder is
begin
	sum<=a xor b xor c;
	carry<=(a and b)or(b and c)or(a and c);
end concurrent;