📄 m511.rpt
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!i11 & !i12 & !i13 & !i14 & !i15 & !i16 & !reset
# !_LC042 & !reset;
-- Node name is ':108' = 'i8'
-- Equation name is 'i8', location is LC050, type is buried.
i8 = DFFE( _EQ010 $ _LC043, GLOBAL( f), VCC, VCC, VCC);
_EQ010 = i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 & !i10 &
!i11 & !i12 & !i13 & !i14 & !i15 & !i16 & _LC043
# _LC043 & reset;
-- Node name is ':107' = 'i9'
-- Equation name is 'i9', location is LC041, type is buried.
i9 = DFFE( _EQ011 $ _LC055, GLOBAL( f), VCC, VCC, VCC);
_EQ011 = i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 & !i10 &
!i11 & !i12 & !i13 & !i14 & !i15 & !i16 & _LC055
# _LC055 & reset;
-- Node name is ':106' = 'i10'
-- Equation name is 'i10', location is LC040, type is buried.
i10 = DFFE( _EQ012 $ _LC062, GLOBAL( f), VCC, VCC, VCC);
_EQ012 = i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 & !i10 &
!i11 & !i12 & !i13 & !i14 & !i15 & !i16 & _LC062
# _LC062 & reset;
-- Node name is ':105' = 'i11'
-- Equation name is 'i11', location is LC061, type is buried.
i11 = DFFE( _EQ013 $ _LC063, GLOBAL( f), VCC, VCC, VCC);
_EQ013 = i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 & !i10 &
!i11 & !i12 & !i13 & !i14 & !i15 & !i16 & _LC063
# _LC063 & reset;
-- Node name is ':104' = 'i12'
-- Equation name is 'i12', location is LC060, type is buried.
i12 = DFFE( _EQ014 $ _LC064, GLOBAL( f), VCC, VCC, VCC);
_EQ014 = i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 & !i10 &
!i11 & !i12 & !i13 & !i14 & !i15 & !i16 & _LC064
# _LC064 & reset;
-- Node name is ':103' = 'i13'
-- Equation name is 'i13', location is LC059, type is buried.
i13 = DFFE( _EQ015 $ !reset, GLOBAL( f), VCC, VCC, VCC);
_EQ015 = i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 & !i10 &
!i11 & !i12 & !i13 & !i14 & !i15 & !i16 & !reset
# !_LC051 & !reset;
-- Node name is ':102' = 'i14'
-- Equation name is 'i14', location is LC058, type is buried.
i14 = DFFE( _EQ016 $ !reset, GLOBAL( f), VCC, VCC, VCC);
_EQ016 = i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 & !i10 &
!i11 & !i12 & !i13 & !i14 & !i15 & !i16 & !reset
# !_LC052 & !reset;
-- Node name is ':101' = 'i15'
-- Equation name is 'i15', location is LC057, type is buried.
i15 = DFFE( _EQ017 $ !reset, GLOBAL( f), VCC, VCC, VCC);
_EQ017 = i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 & !i10 &
!i11 & !i12 & !i13 & !i14 & !i15 & !i16 & !reset
# !_LC054 & !reset;
-- Node name is ':100' = 'i16'
-- Equation name is 'i16', location is LC053, type is buried.
i16 = DFFE( _EQ018 $ _LC056, GLOBAL( f), VCC, VCC, VCC);
_EQ018 = i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 & !i10 &
!i11 & !i12 & !i13 & !i14 & !i15 & !i16 & _LC056
# _LC056 & reset;
-- Node name is '|lpm_add_sub:126|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC018', type is buried
_LC018 = LCELL(!i1 $ !i0);
-- Node name is '|lpm_add_sub:126|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC048', type is buried
_LC048 = LCELL( i2 $ _EQ019);
_EQ019 = i0 & i1;
-- Node name is '|lpm_add_sub:126|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC047', type is buried
_LC047 = LCELL( i3 $ _EQ020);
_EQ020 = i0 & i1 & i2;
-- Node name is '|lpm_add_sub:126|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC046', type is buried
_LC046 = LCELL( i4 $ _EQ021);
_EQ021 = i0 & i1 & i2 & i3;
-- Node name is '|lpm_add_sub:126|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC045', type is buried
_LC045 = LCELL( i5 $ _EQ022);
_EQ022 = i0 & i1 & i2 & i3 & i4;
-- Node name is '|lpm_add_sub:126|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC044', type is buried
_LC044 = LCELL( i6 $ _EQ023);
_EQ023 = i0 & i1 & i2 & i3 & i4 & i5;
-- Node name is '|lpm_add_sub:126|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC042', type is buried
_LC042 = LCELL( i7 $ _EQ024);
_EQ024 = i0 & i1 & i2 & i3 & i4 & i5 & i6;
-- Node name is '|lpm_add_sub:126|addcore:adder|addcore:adder1|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC043', type is buried
_LC043 = LCELL( i8 $ _EQ025);
_EQ025 = i0 & i1 & i2 & i3 & i4 & i5 & i6 & i7;
-- Node name is '|lpm_add_sub:126|addcore:adder|addcore:adder1|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC055', type is buried
_LC055 = LCELL( i9 $ _EQ026);
_EQ026 = i0 & i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8;
-- Node name is '|lpm_add_sub:126|addcore:adder|addcore:adder1|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC062', type is buried
_LC062 = LCELL( i10 $ _EQ027);
_EQ027 = i0 & i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 & i9;
-- Node name is '|lpm_add_sub:126|addcore:adder|addcore:adder1|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC063', type is buried
_LC063 = LCELL( i11 $ _EQ028);
_EQ028 = i0 & i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 & i9 & i10;
-- Node name is '|lpm_add_sub:126|addcore:adder|addcore:adder1|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC064', type is buried
_LC064 = LCELL( i12 $ _EQ029);
_EQ029 = i0 & i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 & i9 & i10 &
i11;
-- Node name is '|lpm_add_sub:126|addcore:adder|addcore:adder1|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC051', type is buried
_LC051 = LCELL( i13 $ _EQ030);
_EQ030 = i0 & i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 & i9 & i10 &
i11 & i12;
-- Node name is '|lpm_add_sub:126|addcore:adder|addcore:adder1|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC052', type is buried
_LC052 = LCELL( i14 $ _EQ031);
_EQ031 = i0 & i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 & i9 & i10 &
i11 & i12 & i13;
-- Node name is '|lpm_add_sub:126|addcore:adder|addcore:adder1|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC054', type is buried
_LC054 = LCELL( i15 $ _EQ032);
_EQ032 = i0 & i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 & i9 & i10 &
i11 & i12 & i13 & i14;
-- Node name is '|lpm_add_sub:126|addcore:adder|addcore:adder2|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC056', type is buried
_LC056 = LCELL( i16 $ _EQ033);
_EQ033 = i0 & i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 & i9 & i10 &
i11 & i12 & i13 & i14 & i15;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Informationd:\so2006\cpld_pro\prog+plus\chip\m+correlation\v+m511\m511.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,986K
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