📄 m511.rpt
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(28) 40 C DFFE + t 0 0 0 1 18 1 23 i10 (:106)
(29) 41 C DFFE + t 0 0 0 1 18 1 24 i9 (:107)
- 50 D DFFE + t 0 0 0 1 18 1 25 i8 (:108)
- 39 C DFFE + t 0 0 0 1 18 1 26 i7 (:109)
- 38 C DFFE + t 0 0 0 1 18 1 27 i6 (:110)
(27) 37 C DFFE + t 0 0 0 1 18 1 28 i5 (:111)
(26) 36 C DFFE + t 0 0 0 1 18 1 29 i4 (:112)
(25) 35 C DFFE + t 0 0 0 1 18 1 30 i3 (:113)
- 34 C DFFE + t 0 0 0 1 18 1 31 i2 (:114)
(24) 33 C DFFE + t 0 0 0 1 18 1 32 i1 (:115)
(21) 17 B DFFE + t 0 0 0 1 1 1 33 i0 (:116)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:d:\so2006\cpld_pro\prog+plus\chip\m+correlation\v+m511\m511.rpt
m511
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----- LC19 f5t
| +--- LC18 |lpm_add_sub:126|addcore:adder|addcore:adder0|result_node1
| | +- LC17 i0
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'B'
LC | | | | A B C D | Logic cells that feed LAB 'B':
LC17 -> - * * | - * * * | <-- i0
Pin
43 -> * - - | - * - - | <-- f
12 -> - - * | - * * * | <-- reset
LC33 -> - * - | - * * * | <-- i1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:d:\so2006\cpld_pro\prog+plus\chip\m+correlation\v+m511\m511.rpt
m511
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC48 |lpm_add_sub:126|addcore:adder|addcore:adder0|result_node2
| +----------------------------- LC47 |lpm_add_sub:126|addcore:adder|addcore:adder0|result_node3
| | +--------------------------- LC46 |lpm_add_sub:126|addcore:adder|addcore:adder0|result_node4
| | | +------------------------- LC45 |lpm_add_sub:126|addcore:adder|addcore:adder0|result_node5
| | | | +----------------------- LC44 |lpm_add_sub:126|addcore:adder|addcore:adder0|result_node6
| | | | | +--------------------- LC42 |lpm_add_sub:126|addcore:adder|addcore:adder0|result_node7
| | | | | | +------------------- LC43 |lpm_add_sub:126|addcore:adder|addcore:adder1|result_node0
| | | | | | | +----------------- LC40 i10
| | | | | | | | +--------------- LC41 i9
| | | | | | | | | +------------- LC39 i7
| | | | | | | | | | +----------- LC38 i6
| | | | | | | | | | | +--------- LC37 i5
| | | | | | | | | | | | +------- LC36 i4
| | | | | | | | | | | | | +----- LC35 i3
| | | | | | | | | | | | | | +--- LC34 i2
| | | | | | | | | | | | | | | +- LC33 i1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC48 -> - - - - - - - - - - - - - - * - | - - * - | <-- |lpm_add_sub:126|addcore:adder|addcore:adder0|result_node2
LC47 -> - - - - - - - - - - - - - * - - | - - * - | <-- |lpm_add_sub:126|addcore:adder|addcore:adder0|result_node3
LC46 -> - - - - - - - - - - - - * - - - | - - * - | <-- |lpm_add_sub:126|addcore:adder|addcore:adder0|result_node4
LC45 -> - - - - - - - - - - - * - - - - | - - * - | <-- |lpm_add_sub:126|addcore:adder|addcore:adder0|result_node5
LC44 -> - - - - - - - - - - * - - - - - | - - * - | <-- |lpm_add_sub:126|addcore:adder|addcore:adder0|result_node6
LC42 -> - - - - - - - - - * - - - - - - | - - * - | <-- |lpm_add_sub:126|addcore:adder|addcore:adder0|result_node7
LC40 -> - - - - - - - * * * * * * * * * | - - * * | <-- i10
LC41 -> - - - - - - - * * * * * * * * * | - - * * | <-- i9
LC39 -> - - - - - * * * * * * * * * * * | - - * * | <-- i7
LC38 -> - - - - * * * * * * * * * * * * | - - * * | <-- i6
LC37 -> - - - * * * * * * * * * * * * * | - - * * | <-- i5
LC36 -> - - * * * * * * * * * * * * * * | - - * * | <-- i4
LC35 -> - * * * * * * * * * * * * * * * | - - * * | <-- i3
LC34 -> * * * * * * * * * * * * * * * * | - - * * | <-- i2
LC33 -> * * * * * * * * * * * * * * * * | - * * * | <-- i1
Pin
43 -> - - - - - - - - - - - - - - - - | - * - - | <-- f
12 -> - - - - - - - * * * * * * * * * | - * * * | <-- reset
LC18 -> - - - - - - - - - - - - - - - * | - - * - | <-- |lpm_add_sub:126|addcore:adder|addcore:adder0|result_node1
LC55 -> - - - - - - - - * - - - - - - - | - - * - | <-- |lpm_add_sub:126|addcore:adder|addcore:adder1|result_node1
LC62 -> - - - - - - - * - - - - - - - - | - - * - | <-- |lpm_add_sub:126|addcore:adder|addcore:adder1|result_node2
LC53 -> - - - - - - - * * * * * * * * * | - - * * | <-- i16
LC57 -> - - - - - - - * * * * * * * * * | - - * * | <-- i15
LC58 -> - - - - - - - * * * * * * * * * | - - * * | <-- i14
LC59 -> - - - - - - - * * * * * * * * * | - - * * | <-- i13
LC60 -> - - - - - - - * * * * * * * * * | - - * * | <-- i12
LC61 -> - - - - - - - * * * * * * * * * | - - * * | <-- i11
LC50 -> - - - - - - * * * * * * * * * * | - - * * | <-- i8
LC17 -> * * * * * * * * * * * * * * * * | - * * * | <-- i0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:d:\so2006\cpld_pro\prog+plus\chip\m+correlation\v+m511\m511.rpt
m511
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC49 f4t
| +----------------------------- LC55 |lpm_add_sub:126|addcore:adder|addcore:adder1|result_node1
| | +--------------------------- LC62 |lpm_add_sub:126|addcore:adder|addcore:adder1|result_node2
| | | +------------------------- LC63 |lpm_add_sub:126|addcore:adder|addcore:adder1|result_node3
| | | | +----------------------- LC64 |lpm_add_sub:126|addcore:adder|addcore:adder1|result_node4
| | | | | +--------------------- LC51 |lpm_add_sub:126|addcore:adder|addcore:adder1|result_node5
| | | | | | +------------------- LC52 |lpm_add_sub:126|addcore:adder|addcore:adder1|result_node6
| | | | | | | +----------------- LC54 |lpm_add_sub:126|addcore:adder|addcore:adder1|result_node7
| | | | | | | | +--------------- LC56 |lpm_add_sub:126|addcore:adder|addcore:adder2|result_node0
| | | | | | | | | +------------- LC53 i16
| | | | | | | | | | +----------- LC57 i15
| | | | | | | | | | | +--------- LC58 i14
| | | | | | | | | | | | +------- LC59 i13
| | | | | | | | | | | | | +----- LC60 i12
| | | | | | | | | | | | | | +--- LC61 i11
| | | | | | | | | | | | | | | +- LC50 i8
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC49 -> * - - - - - - - - - - - - - - - | - - - * | <-- f4t
LC63 -> - - - - - - - - - - - - - - * - | - - - * | <-- |lpm_add_sub:126|addcore:adder|addcore:adder1|result_node3
LC64 -> - - - - - - - - - - - - - * - - | - - - * | <-- |lpm_add_sub:126|addcore:adder|addcore:adder1|result_node4
LC51 -> - - - - - - - - - - - - * - - - | - - - * | <-- |lpm_add_sub:126|addcore:adder|addcore:adder1|result_node5
LC52 -> - - - - - - - - - - - * - - - - | - - - * | <-- |lpm_add_sub:126|addcore:adder|addcore:adder1|result_node6
LC54 -> - - - - - - - - - - * - - - - - | - - - * | <-- |lpm_add_sub:126|addcore:adder|addcore:adder1|result_node7
LC56 -> - - - - - - - - - * - - - - - - | - - - * | <-- |lpm_add_sub:126|addcore:adder|addcore:adder2|result_node0
LC53 -> * - - - - - - - * * * * * * * * | - - * * | <-- i16
LC57 -> * - - - - - - * * * * * * * * * | - - * * | <-- i15
LC58 -> * - - - - - * * * * * * * * * * | - - * * | <-- i14
LC59 -> * - - - - * * * * * * * * * * * | - - * * | <-- i13
LC60 -> * - - - * * * * * * * * * * * * | - - * * | <-- i12
LC61 -> * - - * * * * * * * * * * * * * | - - * * | <-- i11
LC50 -> * * * * * * * * * * * * * * * * | - - * * | <-- i8
Pin
43 -> - - - - - - - - - - - - - - - - | - * - - | <-- f
12 -> * - - - - - - - - * * * * * * * | - * * * | <-- reset
LC43 -> - - - - - - - - - - - - - - - * | - - - * | <-- |lpm_add_sub:126|addcore:adder|addcore:adder1|result_node0
LC40 -> * - * * * * * * * * * * * * * * | - - * * | <-- i10
LC41 -> * * * * * * * * * * * * * * * * | - - * * | <-- i9
LC39 -> * * * * * * * * * * * * * * * * | - - * * | <-- i7
LC38 -> * * * * * * * * * * * * * * * * | - - * * | <-- i6
LC37 -> * * * * * * * * * * * * * * * * | - - * * | <-- i5
LC36 -> * * * * * * * * * * * * * * * * | - - * * | <-- i4
LC35 -> * * * * * * * * * * * * * * * * | - - * * | <-- i3
LC34 -> * * * * * * * * * * * * * * * * | - - * * | <-- i2
LC33 -> * * * * * * * * * * * * * * * * | - * * * | <-- i1
LC17 -> * * * * * * * * * * * * * * * * | - * * * | <-- i0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:d:\so2006\cpld_pro\prog+plus\chip\m+correlation\v+m511\m511.rpt
m511
** EQUATIONS **
f : INPUT;
reset : INPUT;
-- Node name is 'f4t' = ':124'
-- Equation name is 'f4t', type is output
f4t = TFFE( _EQ001, GLOBAL( f), VCC, VCC, VCC);
_EQ001 = !f4t & i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 &
!i10 & !i11 & !i12 & !i13 & !i14 & !i15 & !i16 & !reset
# f4t & i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 &
!i10 & !i11 & !i12 & !i13 & !i14 & !i15 & !i16
# f4t & reset;
-- Node name is 'f5t'
-- Equation name is 'f5t', location is LC019, type is output.
f5t = LCELL( f $ GND);
-- Node name is ':116' = 'i0'
-- Equation name is 'i0', location is LC017, type is buried.
i0 = DFFE( _EQ002 $ GND, GLOBAL( f), VCC, VCC, VCC);
_EQ002 = !i0 & !reset;
-- Node name is ':115' = 'i1'
-- Equation name is 'i1', location is LC033, type is buried.
i1 = DFFE( _EQ003 $ _LC018, GLOBAL( f), VCC, VCC, VCC);
_EQ003 = i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 & !i10 &
!i11 & !i12 & !i13 & !i14 & !i15 & !i16 & _LC018
# _LC018 & reset;
-- Node name is ':114' = 'i2'
-- Equation name is 'i2', location is LC034, type is buried.
i2 = DFFE( _EQ004 $ _LC048, GLOBAL( f), VCC, VCC, VCC);
_EQ004 = i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 & !i10 &
!i11 & !i12 & !i13 & !i14 & !i15 & !i16 & _LC048
# _LC048 & reset;
-- Node name is ':113' = 'i3'
-- Equation name is 'i3', location is LC035, type is buried.
i3 = DFFE( _EQ005 $ _LC047, GLOBAL( f), VCC, VCC, VCC);
_EQ005 = i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 & !i10 &
!i11 & !i12 & !i13 & !i14 & !i15 & !i16 & _LC047
# _LC047 & reset;
-- Node name is ':112' = 'i4'
-- Equation name is 'i4', location is LC036, type is buried.
i4 = DFFE( _EQ006 $ _LC046, GLOBAL( f), VCC, VCC, VCC);
_EQ006 = i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 & !i10 &
!i11 & !i12 & !i13 & !i14 & !i15 & !i16 & _LC046
# _LC046 & reset;
-- Node name is ':111' = 'i5'
-- Equation name is 'i5', location is LC037, type is buried.
i5 = DFFE( _EQ007 $ !reset, GLOBAL( f), VCC, VCC, VCC);
_EQ007 = i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 & !i10 &
!i11 & !i12 & !i13 & !i14 & !i15 & !i16 & !reset
# !_LC045 & !reset;
-- Node name is ':110' = 'i6'
-- Equation name is 'i6', location is LC038, type is buried.
i6 = DFFE( _EQ008 $ !reset, GLOBAL( f), VCC, VCC, VCC);
_EQ008 = i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 & !i10 &
!i11 & !i12 & !i13 & !i14 & !i15 & !i16 & !reset
# !_LC044 & !reset;
-- Node name is ':109' = 'i7'
-- Equation name is 'i7', location is LC039, type is buried.
i7 = DFFE( _EQ009 $ !reset, GLOBAL( f), VCC, VCC, VCC);
_EQ009 = i0 & !i1 & !i2 & !i3 & !i4 & !i5 & !i6 & !i7 & !i8 & !i9 & !i10 &
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