vv.cr.mti

可编程逻辑接口8255并行接口芯片的vhdl描述

D:/Modeltech_eval_6.0d/my_design/8255_2/A8255TB.VHD {1 {vcom -work work -2002 -explicit D:/Modeltech_eval_6.0d/my_design/8255_2/A8255TB.VHD
Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity a8255tb
-- Compiling architecture maintest of a8255tb

} {} {}} D:/Modeltech_eval_6.0d/my_design/8255_2/PORTBOUT.VHD {1 {vcom -work work -2002 -explicit D:/Modeltech_eval_6.0d/my_design/8255_2/PORTBOUT.VHD
Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity portbout
-- Compiling architecture rtl of portbout

} {} {}} D:/Modeltech_eval_6.0d/my_design/8255_2/A8255TOP.VHD {1 {vcom -work work -2002 -explicit D:/Modeltech_eval_6.0d/my_design/8255_2/A8255TOP.VHD
Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity a8255top
-- Compiling architecture struct of a8255top

} {} {}} D:/Modeltech_eval_6.0d/my_design/8255_2/PORTCOUT.VHD {1 {vcom -work work -2002 -explicit D:/Modeltech_eval_6.0d/my_design/8255_2/PORTCOUT.VHD
Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity portcout
-- Compiling architecture rtl of portcout

} {} {}} D:/Modeltech_eval_6.0d/my_design/8255_2/A8255.VHD {1 {vcom -work work -2002 -explicit D:/Modeltech_eval_6.0d/my_design/8255_2/A8255.VHD
Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity a8255
-- Compiling architecture structure of a8255

} {} {}} D:/Modeltech_eval_6.0d/my_design/8255_2/DOUT_MUX.VHD {2 {vcom -work work -2002 -explicit D:/Modeltech_eval_6.0d/my_design/8255_2/DOUT_MUX.VHD
Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity dout_mux
-- Compiling architecture rtl of dout_mux
** Warning: D:/Modeltech_eval_6.0d/my_design/8255_2/DOUT_MUX.VHD(50): Duplicate signals in sensitivity list.

} {} {}} D:/Modeltech_eval_6.0d/my_design/8255_2/PORTAIN.VHD {1 {vcom -work work -2002 -explicit D:/Modeltech_eval_6.0d/my_design/8255_2/PORTAIN.VHD
Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity portain
-- Compiling architecture rtl of portain

} {} {}} D:/Modeltech_eval_6.0d/my_design/8255_2/CNTL_LOG.VHD {1 {vcom -work work -2002 -explicit D:/Modeltech_eval_6.0d/my_design/8255_2/CNTL_LOG.VHD
Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity cntl_log
-- Compiling architecture rtl of cntl_log

} {} {}} D:/Modeltech_eval_6.0d/my_design/8255_2/PORTAOUT.VHD {1 {vcom -work work -2002 -explicit D:/Modeltech_eval_6.0d/my_design/8255_2/PORTAOUT.VHD
Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity portaout
-- Compiling architecture rtl of portaout

} {} {}} D:/Modeltech_eval_6.0d/my_design/8255_2/PORTBIN.VHD {1 {vcom -work work -2002 -explicit D:/Modeltech_eval_6.0d/my_design/8255_2/PORTBIN.VHD
Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity portbin
-- Compiling architecture rtl of portbin

} {} {}}