genxlib_arch.vhd

VHDL代码

  end generate;

end rtl;

-- *********************************************
--  *0004*  round Macro
--  round
--
-- *********************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity round is 
  generic ( 
    iwidth    : integer := 16;
    owidth    : integer := 15;
    has_offset: integer := 0;
    mode      : integer := 0; -- 0: biased, 1: towards zero, 2: towards inf
    delay     : integer :=  1);
  port (
    a       : in std_logic_vector(iwidth-1 downto 0);
    offset  : in  std_logic_vector(OWIDTH-1 downto 0) := (others => '0');
    ra      : out std_logic_vector(OWIDTH-1 downto 0);
    clk     : in std_logic;
    ce      : in std_logic;
    sclr    : in std_logic);
end round;

architecture rtl of round is
  signal rounding_const : std_logic_vector(iwidth-1 downto 0); 
  signal rounding_carry : std_logic;
  signal q              : std_logic_vector(iwidth downto 0); 

begin

  rnd_add : entity work.get_round_addend(rtl)  
    generic map( 
      IWIDTH      => IWIDTH,
      OWIDTH      => OWIDTH,
      has_offset  => has_offset,
      mode        => mode)
    port map(
      msb         => a(IWIDTH-1),
      offset      => offset,
      r_add       => rounding_const,
      r_cy        => rounding_carry);

  adder : entity work.radd_sub_sclr(rtl) 
    generic map ( width => iwidth, delay => delay)   
    port map ( clk => clk, ce => ce, sclr => sclr, 
               c_in => rounding_carry, a => a, b => rounding_const, s => q);

  ra <= q(iwidth-1 downto iwidth-OWIDTH);
end rtl;

-- *********************************************
--  *0005*  mult Macro
--  mult
--
-- *********************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity mult is 
  generic ( 
    IWIDTHA : integer:=18;
    IWIDTHB : integer:=18;
    delay   : integer:=2);
  port (
    a       : in std_logic_vector(IWIDTHA-1 downto 0);
    b       : in std_logic_vector(IWIDTHB-1 downto 0);
    p       : out std_logic_vector(IWIDTHA+IWIDTHB-1 downto 0);
    clk     : in std_logic;
    ce      : in std_logic;
    sclr    : in std_logic);

  attribute register_balancing: string; 
  attribute register_balancing of mult: entity is "yes";
  attribute mult_style: string;
  attribute mult_style of mult: entity is "pipe_block"; 
end mult;

architecture rtl of mult is  

  signal c : std_logic_vector(IWIDTHA+IWIDTHB-1 downto 0);

begin

  c <= a * b;

  reg : entity work.delay_sclr(rtl) 
    generic map ( width => IWIDTHA+IWIDTHB, delay => delay)   
    port map ( clk => clk, ce => ce, sclr => sclr, d => c, q => p);

end rtl;

-- *********************************************
--  *0006*  mac Macro
--  mac
--
-- *********************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity mac is            -- this module calculates p = round(a*b)+c
  generic (              -- p = reg( reg(reg(a) * reg(b)) + reg(c)) 
    IWIDTHA     : integer:=16;
    IWIDTHB     : integer:=16;
    OWIDTH      : integer:=16;
    ROUND_MODE  : integer:= 0; -- 0: biased, 1: towards zero, 2: towards inf
    HAS_C       : integer:= 0;
    CREG        : integer:= 0);
  port (
    a           : in std_logic_vector(IWIDTHA-1 downto 0);
    b           : in std_logic_vector(IWIDTHB-1 downto 0);
    c           : in std_logic_vector(OWIDTH-1 downto 0);
    p           : out std_logic_vector(OWIDTH-1 downto 0);
    clk         : in std_logic;
    ce          : in std_logic;
    sclr        : in std_logic);

  attribute register_balancing: string; 
  attribute register_balancing of mac: entity is "yes";
  attribute mult_style: string;
  attribute mult_style of mac: entity is "pipe_block"; 
  attribute use_dsp48: string; 
  attribute use_dsp48 of mac: entity is "yes"; 
  
end mac;

architecture rtl of mac is  

  signal rounding_const : std_logic_vector(IWIDTHA+IWIDTHB-1 downto 0); -- rounding constant (optional) combined with input c (optional)
  signal add_c_rnd_const: std_logic_vector(IWIDTHA+IWIDTHB-1 downto 0); -- optionally registered version of rounding_const
  signal rounding_carry : std_logic;
  signal r_cy_in 		    : std_logic := '0';
  signal ar    : std_logic_vector(IWIDTHA-1 downto 0) := (others => '0');
  signal br    : std_logic_vector(IWIDTHB-1 downto 0) := (others => '0');
  signal cr    : std_logic_vector(IWIDTHA+IWIDTHB-1 downto 0) := (others => '0'); -- registered version of rounding_const
  signal pr    : std_logic_vector(IWIDTHA+IWIDTHB-1 downto 0) := (others => '0');
  signal mac   : std_logic_vector(IWIDTHA+IWIDTHB-1 downto 0) := (others => '0');
  signal ones  : std_logic_vector(OWIDTH-1 downto 0) := (others => '1');

  attribute keep_hierarchy : string; 
  attribute keep_hierarchy of rtl: architecture is "yes"; 

begin

  yes_creg: if (CREG /= 0) generate add_c_rnd_const <= cr; end generate;
  no_creg : if (CREG = 0)  generate add_c_rnd_const <= rounding_const; end generate;
  
  rnd_add : entity work.get_round_addend(rtl)  
    generic map( 
      IWIDTH      => IWIDTHA+IWIDTHB,
      OWIDTH      => OWIDTH,
      has_offset  => HAS_C,
      mode        => ROUND_MODE)
    port map(
      msb         => r_cy_in,
      offset      => c,
      r_add       => rounding_const,
      r_cy        => rounding_carry);

  clk_process: process(clk)
  begin
    if (clk'event and clk = '1') then
      if (sclr = '1') then  
        ar      <= (others => '0');
        br      <= (others => '0');
        cr      <= (others => '0');
        pr      <= (others => '0');        
        r_cy_in <= '0';        
        mac     <= (others => '0');
       elsif (ce = '1') then 
        r_cy_in <= ar(IWIDTHA-1) xor br(IWIDTHB-1);
        mac <= pr +  add_c_rnd_const + rounding_carry;
        pr <= ar*br;
        ar <= a;
        br <= b;
        cr <= rounding_const;
      end if;
    end if;
  end process;

  p <= mac(IWIDTHA+IWIDTHB-1 downto IWIDTHA+IWIDTHB-OWIDTH);

end;

-- *********************************************
--  simple mac Macro with C input
--  input C is registered !
--
-- *********************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity mac_c is             -- this module calculates mac = a*b+c
  generic (                 -- p = reg( reg(reg(a) * reg(b)) + reg(c)) 
    IWIDTHA     : integer:=16;
    IWIDTHB     : integer:=16;
    OWIDTH      : integer:=16);
  port (
    a           : in std_logic_vector(IWIDTHA-1 downto 0);
    b           : in std_logic_vector(IWIDTHB-1 downto 0);
    c           : in std_logic_vector(IWIDTHA+IWIDTHB-1 downto 0);
    p           : out std_logic_vector(OWIDTH-1 downto 0);
    clk         : in std_logic;
    ce          : in std_logic;
    sclr        : in std_logic);

  attribute register_balancing: string; 
  attribute register_balancing of mac_c: entity is "yes";
  attribute mult_style: string;
  attribute mult_style of mac_c: entity is "pipe_block"; 
  attribute use_dsp48: string; 
  attribute use_dsp48 of mac_c: entity is "yes"; 
  
end mac_c;

architecture rtl of mac_c is  

  signal ar    : std_logic_vector(IWIDTHA-1 downto 0) := (others => '0');
  signal br    : std_logic_vector(IWIDTHB-1 downto 0) := (others => '0');
  signal cr    : std_logic_vector(IWIDTHA+IWIDTHB-1 downto 0) := (others => '0'); -- registered version of rounding_const
  signal pr    : std_logic_vector(IWIDTHA+IWIDTHB-1 downto 0) := (others => '0');
  signal mac   : std_logic_vector(IWIDTHA+IWIDTHB-1 downto 0) := (others => '0');

begin

  clk_process: process(clk)
  begin
    if (clk'event and clk = '1') then
      if (sclr = '1') then  
        ar      <= (others => '0');
        br      <= (others => '0');
        cr      <= (others => '0');
        pr      <= (others => '0');        
        mac     <= (others => '0');
       elsif (ce = '1') then 
        mac <= pr +  cr;
        pr <= ar*br;
        ar <= a;
        br <= b;
        cr <= c;
      end if;
    end if;
  end process;

  p <= mac(IWIDTHA+IWIDTHB-1 downto IWIDTHA+IWIDTHB-OWIDTH);

end;

-- *********************************************
--  simple mac Macro with P cascade input
--  input Pcin is not registered !
--
-- *********************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity mac_pc is             -- this module calculates mac = a*b+c
  generic (                 -- p = reg( reg(reg(a) * reg(b)) + reg(c)) 
    IWIDTHA     : integer:=16;
    IWIDTHB     : integer:=16;
    OWIDTH      : integer:=16);
  port (
    a           : in std_logic_vector(IWIDTHA-1 downto 0);
    b           : in std_logic_vector(IWIDTHB-1 downto 0);
    pcin        : in std_logic_vector(IWIDTHA+IWIDTHB-1 downto 0);
    p           : out std_logic_vector(OWIDTH-1 downto 0);
    clk         : in std_logic;
    ce          : in std_logic;
    sclr        : in std_logic);

  attribute register_balancing: string; 
  attribute register_balancing of mac_pc : entity is "yes";
  attribute mult_style: string;
  attribute mult_style of mac_pc : entity is "pipe_block"; 
  attribute use_dsp48: string; 
  attribute use_dsp48 of mac_pc : entity is "yes"; 
  
end mac_pc;

architecture rtl of mac_pc is  

  signal ar    : std_logic_vector(IWIDTHA-1 downto 0) := (others => '0');
  signal br    : std_logic_vector(IWIDTHB-1 downto 0) := (others => '0');
  signal pr    : std_logic_vector(IWIDTHA+IWIDTHB-1 downto 0) := (others => '0');
  signal mac   : std_logic_vector(IWIDTHA+IWIDTHB-1 downto 0) := (others => '0');

begin

  clk_process: process(clk)
  begin
    if (clk'event and clk = '1') then
      if (sclr = '1') then  
        ar      <= (others => '0');
        br      <= (others => '0');
        pr      <= (others => '0');        
        mac     <= (others => '0');
       elsif (ce = '1') then 
        mac <= pr +  pcin;
        pr <= ar*br;
        ar <= a;
        br <= b;
      end if;
    end if;
  end process;

  p <= mac(IWIDTHA+IWIDTHB-1 downto IWIDTHA+IWIDTHB-OWIDTH);

end;

-- *********************************************
--  *0007*  max_sat Macro
--  max_sat
--
-- *********************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity max_sat is 
  generic ( 
    width  : integer:= 16;
    delay   : integer:= 1 );
  port (
    a       : in std_logic_vector(width-1 downto 0);
    max     : in std_logic_vector(width-1 downto 0);
    ma      : out std_logic_vector(width-1 downto 0);
    clk     : in std_logic;
    ce      : in std_logic;
    sclr    : in std_logic);

  attribute register_balancing: string; 
  attribute register_balancing of max_sat: entity is "yes";
end max_sat;

architecture rtl of max_sat is
  signal c : std_logic_vector(width-1 downto 0);
begin
  c <=  max when (a > max) else a;
  reg : entity work.delay_sclr(rtl) 
    generic map ( width => width, delay => delay)   
    port map ( clk => clk, ce => ce, sclr => sclr, d => c, q => ma);
end rtl;

-- *********************************************
--  *0008*  min_sat Macro
--  min_sat
--
-- *********************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity min_sat is 
  generic ( 
    width   : integer:=16;
    delay   : integer:=1);
  port (
    a       : in std_logic_vector(width-1 downto 0);
    min     : in std_logic_vector(width-1 downto 0);
    ma      : out std_logic_vector(width-1 downto 0);
    clk     : in std_logic;
    ce      : in std_logic;
    sclr    : in std_logic );
  attribute register_balancing: string; 
  attribute register_balancing of min_sat: entity is "yes";
end min_sat;

architecture rtl of min_sat is
  signal c : std_logic_vector(width-1 downto 0);
begin
  c <=  min when (a < min) else a;
  reg : entity work.delay_sclr(rtl) 
    generic map ( width => width, delay => delay)   
    port map ( clk => clk, ce => ce, sclr => sclr, d => c, q => ma);

end rtl;