xil_ycrcb2rgb_sg_wrap.vhd

VHDL代码

--*******************************************************************
-- Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
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-- Xilinx is providing this design, code, or information
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-- code, or information as one possible implementation of
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-- This copyright and support notice must be retained as part
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-- All rights reserved.
--
-- Title - Xil_YCrCb2RGB.vhd
-- Author(s) - GZ & WCC, Xilinx
-- Creation - 7 Dec 2005
--
-- $RCSfile: Xil_YCrCb2RGB.vhd,v $ $Revision: 1.8 $ $Date: 2006/01/19 19:55:41 $
--
-- ************************************************************************
--  *008*   YCrCb2RGB Macro
--
-- Description: Color Space Converter (RGB to YCrCb)
--
-- Generalized conversion:
-- Y  =   |   AC    (1-AC-BC)    BC   |   |R|    |Yoffset| 
-- Cr = CC| (1-AC)  (AC+BC-1)   -BC   | * |G| +  |Coffset|
-- Cb = CD|  -AC    (AC+BC-1)  (1-BC) |   |B|    |Coffset|
--
--
-- Refactored format conversion:
-- Y  = AC*R + (1-AC-BC)*G + BC*B + Yoffset 
-- Cr = CC*(R-Y) +  Coffset
-- Cb = CD*(B-Y) +  Coffset

-- ITU 601 (SDTV):
-- if RGB data is between 0 and 255 
--
-- Y  =  0.299 * R' + 0.587 * G' + 0.114 * B' + 0   
-- Cr =  0.5   * R' - 0.419 * G' - 0.081 * B' + 0.5
-- Cb = -0.169 * R' - 0.331 * G' + 0.5   * B' + 0.5
--
---------------------------------------------------------------------
-- Refactoring:
-- if RGB data is between 0 and 255 (R'G'B' are gamma corrected)
--
-- Y   = 0.299 * (R' - G') + G' + 0.114 * (B' - G') 
-- Cr  = 0.713 * (R' - Y') + 0.5
-- Cb  = 0.564 * (B' - Y') + 0.5
--
-- ******************************************************************  
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all; 

LIBRARY work;
USE work.color_space_pkg.all;

LIBRARY work;
USE work.genxlib_utils.ALL;

entity Xil_YCrCb2RGB_sg is   
  generic ( 
    FAMILY_HAS_MAC: integer:= 1;
    FABRIC_ADDS   : integer:= 1; -- Adders are implemented using logic fabric based adders
    IWIDTH        : integer:= 9;
    CWIDTH        : integer:= 13; -- Coefficients are signed, CWIDTH.CWIDTH-2 format
    MWIDTH        : integer:= 23; -- ONLY FOR NON-V4: Controls bits witheld after mults. 
    OWIDTH        : integer:= 9;  -- OTHERWISE (default) IWIDTH+CWIDTH+1;
    RGBMAX        : integer:= 255;
    RGBMIN        : integer:= 0;
    ACOEF         : integer:= 2872;   --    1.4023   *pow2(CWIDTH-2) 
    BCOEF         : integer:= -1461;  --    -0.7133  *pow2(CWIDTH-2) 
    CCOEF         : integer:= -703;   --    -0.3434  *pow2(CWIDTH-2) 
    DCOEF         : integer:= 3630;   --    1.7724   *pow2(CWIDTH-2) 
    ROFFSET       : integer:= -366592;  -- Should be MWIDTH bits wide 
    GOFFSET       : integer:= 278016;   
    BOFFSET       : integer:= -463616;
    HAS_CLIP      : integer:= 1; 
    HAS_CLAMP     : integer:= 1);     
  port (                               
    Y             : in std_logic_vector(IWIDTH-1 downto 0);  -- Y  = a(R-G) + G + b(B-G)
    Cr            : in std_logic_vector(IWIDTH-1 downto 0);  -- Cr = d(R-Y)  
    Cb            : in std_logic_vector(IWIDTH-1 downto 0);  -- Cb = c(B-Y)
    R             : out std_logic_vector(OWIDTH-1 downto 0);   
    G             : out std_logic_vector(OWIDTH-1 downto 0);
    B             : out std_logic_vector(OWIDTH-1 downto 0);
    V_SYNC_in     : in std_logic := '0';
    H_SYNC_in     : in std_logic := '0';
    PIX_EN_in     : in std_logic := '1';
    V_SYNC_out    : out std_logic;
    H_SYNC_out    : out std_logic;
    PIX_EN_out    : out std_logic;
    clk           : in std_logic;
    ce            : in std_logic := '1';
    en            : in std_logic := '1';
    rst           : in std_logic := '0');
end Xil_YCrCb2RGB_sg;    

architecture rtl of Xil_YCrCb2RGB_sg is            

  component Xil_YCrCb2RGB is   
    generic ( 
      FAMILY_HAS_MAC: integer:= 1;
      FABRIC_ADDS   : integer:= 1; -- Adders are implemented using logic fabric based adders
      IWIDTH        : integer:= 9;
      CWIDTH        : integer:= 13; -- Coefficients are signed, CWIDTH.CWIDTH-2 format
      MWIDTH        : integer:= 23; -- ONLY FOR NON-V4: Controls bits witheld after mults. 
      OWIDTH        : integer:= 9;  -- OTHERWISE (default) IWIDTH+CWIDTH+1;
      RGBMAX        : integer:= 255;
      RGBMIN        : integer:= 0;
      ACOEF         : integer:= 2872;   --    1.4023   *pow2(CWIDTH-2) 
      BCOEF         : integer:= -1461;  --    -0.7133  *pow2(CWIDTH-2) 
      CCOEF         : integer:= -703;   --    -0.3434  *pow2(CWIDTH-2) 
      DCOEF         : integer:= 3630;   --    1.7724   *pow2(CWIDTH-2) 
      ROFFSET       : integer:= -366592;  -- Should be MWIDTH bits wide 
      GOFFSET       : integer:= 278016;   
      BOFFSET       : integer:= -463616;
      HAS_CLIP      : integer:= 1; 
      HAS_CLAMP     : integer:= 1);     
    port (                               
      Y             : in std_logic_vector(IWIDTH-1 downto 0);  -- Y  = a(R-G) + G + b(B-G)
      Cr            : in std_logic_vector(IWIDTH-1 downto 0);  -- Cr = d(R-Y)  
      Cb            : in std_logic_vector(IWIDTH-1 downto 0);  -- Cb = c(B-Y)
      R             : out std_logic_vector(OWIDTH-1 downto 0);   
      G             : out std_logic_vector(OWIDTH-1 downto 0);
      B             : out std_logic_vector(OWIDTH-1 downto 0);
      V_SYNC_in     : in std_logic := '0';
      H_SYNC_in     : in std_logic := '0';
      PIX_EN_in     : in std_logic := '1';
      V_SYNC_out    : out std_logic;
      H_SYNC_out    : out std_logic;
      PIX_EN_out    : out std_logic;
      clk           : in std_logic;
      ce            : in std_logic := '0';
      sclr          : in std_logic := '0');
  end component;

  signal ce_net: std_logic;

begin

  ce_net <= ce and en;
  
  colorspaceYCrCb2RGB: Xil_YCrCb2RGB
    generic map (
      FAMILY_HAS_MAC  => FAMILY_HAS_MAC,
      FABRIC_ADDS     => FABRIC_ADDS   ,
      IWIDTH          => IWIDTH        , 
      CWIDTH          => CWIDTH        ,
      MWIDTH          => MWIDTH        ,
      OWIDTH          => OWIDTH        ,
      RGBMAX          => RGBMAX        ,
      RGBMIN          => RGBMIN        ,
      ROFFSET         => ROFFSET       ,
      GOFFSET         => GOFFSET       ,
      BOFFSET         => BOFFSET       ,
      ACOEF           => ACOEF         ,
      BCOEF           => BCOEF         ,
      CCOEF           => CCOEF         ,
      DCOEF           => DCOEF         ,
      HAS_CLIP        => HAS_CLIP      ,
      HAS_CLAMP       => HAS_CLAMP)
    port map (
      R               => R,
      G               => G,
      B               => B,
      V_SYNC_in       => V_SYNC_in,
      H_SYNC_in       => H_SYNC_in,
      PIX_EN_in       => PIX_EN_in,
      V_SYNC_out      => V_SYNC_out,
      H_SYNC_out      => H_SYNC_out,
      PIX_EN_out      => PIX_EN_out,
      clk             => clk,
      ce              => ce_net,
      sclr            => rst,
      Y               => Y,
      Cr              => Cr,
      Cb              => Cb );
end rtl;