xil_ycrcb2rgb_config.m

VHDL代码

function Xil_colorspaceYCrCb2RGB_config(this_block)

  % Revision History:
  %
  %   18-Sep-2005  (23:07 hours):
  %     Original code was machine generated by Xilinx's System Generator after parsing
  %     D:\VideoBlockset\development\HDL_src\ColorSpace\testbench\Xil_colorspaceYCrCb2RGB.vhd
  %
  %
  mybb      = this_block.blockName;
  color_sub = get_param(mybb,'Parent');
  param_a = str2num(get_param(color_sub, 'coefA'));
  param_b = str2num(get_param(color_sub, 'coefB'));
  param_d = str2num(get_param(color_sub, 'coefC'));
  param_c = str2num(get_param(color_sub, 'coefD'));
  rgbmax  = str2num(get_param(color_sub, 'rgbmax'));
  rgbmin  = str2num(get_param(color_sub, 'rgbmin'));
  clip    = strcmp(get_param(color_sub, 'has_clip'),'on');
  clamp   = strcmp(get_param(color_sub, 'has_clamp'),'on');
  yoffset = str2num(get_param(color_sub, 'yoffset'));
  coffset = str2num(get_param(color_sub, 'coffset'));
  in_bits = str2num(get_param(color_sub, 'in_bits'));
  out_bits= str2num(get_param(color_sub, 'out_bits'));
  c_bits  = str2num(get_param(color_sub, 'c_bits'));
  m_bits  = str2num(get_param(color_sub, 'm_bits'));
  fabric_adds = double(strcmp(get_param(color_sub, 'fabric_adds'),'on'));

  this_block.setTopLevelLanguage('VHDL');
  this_block.setEntityName('Xil_YCrCb2RGB_sg');

  % System Generator has to assume that your entity  has a combinational feed through; 
  this_block.tagAsCombinational;

  this_block.addSimulinkInport('Y');
  this_block.addSimulinkInport('Cr');
  this_block.addSimulinkInport('Cb');
  this_block.addSimulinkInport('V_SYNC_in');
  this_block.addSimulinkInport('H_SYNC_in');
  this_block.addSimulinkInport('PIX_EN_in');
  this_block.addSimulinkInport('en');
  this_block.addSimulinkInport('rst');
  this_block.addSimulinkOutport('R');
  this_block.addSimulinkOutport('G');
  this_block.addSimulinkOutport('B');
  this_block.addSimulinkOutport('V_SYNC_out');
  this_block.addSimulinkOutport('H_SYNC_out');
  this_block.addSimulinkOutport('PIX_EN_out');

  vsyncout_port = this_block.port('V_SYNC_out');
  vsyncout_port.setType('UFix_1_0');
  vsyncout_port.useHDLVector(false);
  hsyncout_port = this_block.port('H_SYNC_out');
  hsyncout_port.setType('UFix_1_0');
  hsyncout_port.useHDLVector(false);
  pixenout_port = this_block.port('PIX_EN_out');
  pixenout_port.setType('UFix_1_0');
  pixenout_port.useHDLVector(false);
  
  if (this_block.inputTypesKnown)

    % FAMILY information passed down from sysgen 8.1.
    % The following separation is necessary because the VHDL source is
    % different for v4 and non-v4 cases
    % v4 = strcmp(family, '"virtex4"');
    % v4 = double(strcmp(get_param(color_sub, 'is_v4'),'on'));
    v4 = double(strcmp(lower(this_block.getDeviceFamilyName()), 'virtex4'));

    % do input type checking, dynamic output type and generic setup in this code block.
    if (this_block.port('V_SYNC_in').width ~= 1)
      this_block.setError('Input data type for port "V_SYNC_in" must have width=1');
    end
    this_block.port('V_SYNC_in').useHDLVector(false);

    if (this_block.port('H_SYNC_in').width ~= 1)
      this_block.setError('Input data type for port "H_SYNC_in" must have width=1');
    end
    this_block.port('H_SYNC_in').useHDLVector(false);

    if (this_block.port('PIX_EN_in').width ~= 1)
      this_block.setError('Input data type for port "PIX_EN_in" must have width=1');
    end
    this_block.port('PIX_EN_in').useHDLVector(false);

    if (this_block.port('en').width ~= 1)
      this_block.setError('Input data type for port "en" must have width=1');
    end
    this_block.port('en').useHDLVector(false);

    if (this_block.port('rst').width ~= 1)
      this_block.setError('Input data type for port "rst" must have width=1');
    end
    this_block.port('rst').useHDLVector(false);

    if (this_block.port('Y').width  ~= in_bits) error('Width of port Y not equal with input bits specified through GUI'); end
    if (this_block.port('Cr').width ~= in_bits) error('Width of port Cr not equal with input bits specified through GUI'); end
    if (this_block.port('Cb').width ~= in_bits) error('Width of port Cb not equal with input bits specified through GUI'); end
    this_block.port('R').width = out_bits;
    this_block.port('G').width = out_bits;
    this_block.port('B').width = out_bits;
    this_block.port('V_SYNC_out').width = 1;
    this_block.port('H_SYNC_out').width = 1;
    this_block.port('PIX_EN_out').width = 1;

    coef_a = round( pow2(c_bits-2)* 1/param_c);
    coef_b = round( pow2(c_bits-2)* (-param_a)/param_c*1/(1-param_a-param_b));
    coef_c = round( pow2(c_bits-2)* (-param_b)/param_d*1/(1-param_a-param_b));
    coef_d = round( pow2(c_bits-2)* 1/param_d);

    rounding_const = pow2(m_bits-out_bits-2); % 0.5 in m_bits.o_bits representation
    scale_m = pow2(in_bits + c_bits - m_bits);
   
    roffset = round((rounding_const - (coef_a*coffset          + yoffset)/scale_m)/(1+v4)); 
    goffset = round((rounding_const - ((coef_b+coef_c)*coffset + yoffset)/scale_m)/(1+v4)); 
    boffset = round((rounding_const - (coef_d*coffset          + yoffset)/scale_m)/(1+v4)); 

    this_block.addGeneric('family_has_mac', v4); 
    this_block.addGeneric('fabric_adds', fabric_adds);    
    this_block.addGeneric('iwidth', in_bits);
    this_block.addGeneric('cwidth', c_bits );
    this_block.addGeneric('mwidth', m_bits );
    this_block.addGeneric('owidth', out_bits);
    this_block.addGeneric('acoef', coef_a);
    this_block.addGeneric('bcoef', coef_b);
    this_block.addGeneric('ccoef', coef_c);
    this_block.addGeneric('dcoef', coef_d);
    this_block.addGeneric('has_clip', 'integer', num2str(clip));
    this_block.addGeneric('has_clamp', 'integer', num2str(clamp));
    this_block.addGeneric('rgbmin', rgbmin);
    this_block.addGeneric('rgbmax', rgbmax);
    this_block.addGeneric('roffset', roffset );
    this_block.addGeneric('goffset', goffset );   
    this_block.addGeneric('boffset', boffset );
  end  
  % -----------------------------

  % -----------------------------
   if (this_block.inputRatesKnown)
     setup_as_single_rate(this_block,'clk','ce')
   end  % if(inputRatesKnown)
  % -----------------------------

  this_block.addFile('../GenXlib_utils.vhd');
  this_block.addFile('../GenXlib_arch.vhd');
  this_block.addFile('../color_space_pkg.vhd');
  this_block.addFile('../Xil_YCrCb2RGB.vhd');
  this_block.addFile('Xil_YCrCb2RGB_sg_wrap.vhd');
return;


% ------------------------------------------------------------

function setup_as_single_rate(block,clkname,cename) 
  inputRates = block.inputRates; 
  uniqueInputRates = unique(inputRates); 
  if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) 
    block.setError('The inputs to this block cannot all be constant.'); 
    return; 
  end 
  if (uniqueInputRates(end) == Inf) 
     hasConstantInput = true; 
     uniqueInputRates = uniqueInputRates(1:end-1); 
  end 
  if (length(uniqueInputRates) ~= 1) 
    block.setError('The inputs to this block must run at a single rate.'); 
    return; 
  end 
  theInputRate = uniqueInputRates(1); 
  for i = 1:block.numSimulinkOutports 
     block.outport(i).setRate(theInputRate); 
  end 
  block.addClkCEPair(clkname,cename,theInputRate); 
  return; 

% ------------------------------------------------------------