xil_ycrcb2rgb.vhd

VHDL代码

        fabric=> 1)   
      port map (
        a     => Acoef_by_Cr(IWIDTH+CWIDTH-1 downto IWIDTH+CWIDTH-MWIDTH),
        b     => Roffsetvec,
        s     => Acoef_by_Cr_rnd,
        c_in  => logic0,
        clk   => clk,
        ce    => ce,
        sclr  => sclr);   

    round_bCr : entity work.radd_sub_sclr(rtl)   -- Adding and Rounding of Ccoef_by_Cr and Bcoef_by_Cb_rnd using one adder
      generic map ( 
        width => MWIDTH, 
        add   => true,
        fabric=> 1)   
      port map (
        a     => Bcoef_by_Cr(IWIDTH+CWIDTH-1 downto IWIDTH+CWIDTH-MWIDTH),
        b     => Ccoef_by_Cb_rnd(MWIDTH-1 downto 0),
        s     => Bcoef_by_Cr_rnd,
        c_in  => logic0,
        clk   => clk,
        ce    => ce,
        sclr  => sclr);   

    round_cCb : entity work.radd_sub_sclr(rtl)   -- Rounding and offset compensating G with one adder
      generic map ( 
        width => MWIDTH, 
        add   => true,
        fabric=> 1)   
      port map (
        a     => Ccoef_by_Cb(IWIDTH+CWIDTH-1 downto IWIDTH+CWIDTH-MWIDTH),
        b     => Goffsetvec,
        s     => Ccoef_by_Cb_rnd,
        c_in  => logic0,
        clk   => clk,
        ce    => ce,
        sclr  => sclr);   

    round_dCb : entity work.radd_sub_sclr(rtl)   -- Rounding and offset compensating G with one adder
      generic map ( 
        width => MWIDTH, 
        add   => true,
        fabric=> 1)   
      port map (
        a     => Dcoef_by_Cb(IWIDTH+CWIDTH-1 downto IWIDTH+CWIDTH-MWIDTH),
        b     => Boffsetvec,
        s     => Dcoef_by_Cb_rnd,
        c_in  => logic0,
        clk   => clk,
        ce    => ce,
        sclr  => sclr);   

  end generate;

  v4: if (FAMILY_HAS_MAC = 1) generate  -- DSP48 based implementation
    mult_aCr: entity work.mac(rtl)              -- ACOEFF * Cr + Roffsetvec
      generic map (                                -- offset contains rounding const
        IWIDTHA   => IWIDTH+1, 
        IWIDTHB   => CWIDTH,   
        OWIDTH    => MWIDTH,
        ROUND_MODE=> 0,
        HAS_C     => 1)
      port map (
        clk       => clk,
        ce        => ce,
        sclr      => sclr,
        a         => Cr_delay,
        b         => ACOEFvec,
        c         => Roffsetvec,
        p         => Acoef_by_Cr_rnd(MWIDTH downto 1));
    -- sign extension for simulation (v4 results are the same as s3_v2_v2p)
    --Acoef_by_Cr_rnd(IWIDTH+CWIDTH) <= Acoef_by_Cr_rnd(IWIDTH+CWIDTH-1); 
  
    mult_BCr: entity work.mac(rtl)              -- BCOEFF * Cr + CCOEFF * Cb + Goffsetvec
      generic map ( 
        IWIDTHA   => IWIDTH+1, 
        IWIDTHB   => CWIDTH,   
        OWIDTH    => MWIDTH,
        ROUND_MODE=> 0,
        CREG      => 0,                         -- use Pcascade chain
        HAS_C     => 1)
      port map (
        clk       => clk,
        ce        => ce,
        sclr      => sclr,
        a         => Cr_delay,
        b         => BCOEFvec,
        c         => Ccoef_by_Cb_rnd(MWIDTH downto 1),
        p         => Bcoef_by_Cr_rnd(MWIDTH downto 1));
    -- sign extension for simulation (v4 results are the same as s3_v2_v2p)
    --Bcoef_by_Cr_rnd(IWIDTH+CWIDTH) <= Bcoef_by_Cr_rnd(IWIDTH+CWIDTH-1); 

    mult_cCb: entity work.mac(rtl)              -- CCOEFF * Cb + Goffsetvec
      generic map (                                -- offset contains rounding const
        IWIDTHA   => IWIDTH+1, 
        IWIDTHB   => CWIDTH,   
        OWIDTH    => MWIDTH,
        ROUND_MODE=> 0,
        HAS_C     => 1)
      port map (
        clk       => clk,
        ce        => ce,
        sclr      => sclr,
        a         => Cb_unsign,
        b         => CCOEFvec,
        c         => Goffsetvec,
        p         => Ccoef_by_Cb_rnd(MWIDTH downto 1));
    -- sign extension for simulation (v4 results are the same as s3_v2_v2p)
--    Ccoef_by_Cb_rnd(IWIDTH+CWIDTH) <= Ccoef_by_Cb_rnd(IWIDTH+CWIDTH-1); 

    mult_DCb: entity work.mac(rtl)              -- DCOEFF * Cb + Boffsetvec
      generic map (                                -- offset contains rounding const
        IWIDTHA   => IWIDTH+1, 
        IWIDTHB   => CWIDTH,   
        OWIDTH    => MWIDTH,
        ROUND_MODE=> 0,
        HAS_C     => 1)
      port map (
        clk       => clk,
        ce        => ce,
        sclr      => sclr,
        a         => Cb_delay,
        b         => DCOEFvec,
        c         => Boffsetvec,
        p         => Dcoef_by_Cb_rnd(MWIDTH downto 1));
    -- sign extension for simulation (v4 results are the same as s3_v2_v2p)
    --Dcoef_by_Cb_rnd(IWIDTH+CWIDTH) <= Dcoef_by_Cb_rnd(IWIDTH+CWIDTH-1); 

--    Acoef_by_Cr_rnd(MWIDTH) <= Acoef_by_Cr_rnd(MWIDTH-1);
--    Bcoef_by_Cr_rnd(MWIDTH) <= Bcoef_by_Cr_rnd(MWIDTH-1);
--    Ccoef_by_Cb_rnd(MWIDTH) <= Ccoef_by_Cb_rnd(MWIDTH-1);
--    Dcoef_by_Cb_rnd(MWIDTH) <= Dcoef_by_Cb_rnd(MWIDTH-1);
        
    Acoef_by_Cr_rnd(0) <= '0';
    Bcoef_by_Cr_rnd(0) <= '0';
    Ccoef_by_Cb_rnd(0) <= '0';
    Dcoef_by_Cb_rnd(0) <= '0';
  end generate;

--------------------------------------------------------------------
-- Add Y component
--------------------------------------------------------------------

  del_Y : entity work.delay(rtl)  -- Delay matching: y is delayed so it can be combined with rounded signals  
    generic map ( 
      width => IWIDTH, 
      delay => 4) -- 3+FAMILY_HAS_MAC -- ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS)+MULT_DELAY(FAMILY_HAS_MAC)
    port map (
      clk   => clk,
      d     => Y,  
      q     => y_delay,
      ce    => ce);    

  connect_Y: if (IWIDTH=OWIDTH) generate
    Y_padded(IWIDTH-1 downto 0) <= y_delay;
  end generate;

  padd_Y: if (IWIDTH<OWIDTH) generate
    Y_padded(OWIDTH-1 downto OWIDTH-IWIDTH) <= y_delay;
    Y_padded(OWIDTH-IWIDTH-1 downto 0) <= (others => '0'); 
  end generate;

  truncate_Y: if (IWIDTH>OWIDTH) generate
    Y_padded(OWIDTH-1 downto 0) <= y_delay(IWIDTH-1 downto IWIDTH-OWIDTH);
  end generate;
  
  Y_padded(OWIDTH) <= '0'; -- Makes sure Y_padded is unsigned positive 
  
  add_R : entity work.radd_sub_sclr(rtl)   
    generic map ( 
      width     => OWIDTH+1, 
      add       => true,
      a_signed  => true,
      b_signed  => false,
      delay     => 2-FABRIC_ADDS,
      fabric    => FABRIC_ADDS)   
    port map (
      clk   => clk,
      a     => Acoef_by_Cr_rnd(MWIDTH-2 downto MWIDTH-OWIDTH-2),
      b     => Y_padded,
      s     => R_int,
      c_in  => logic0,
      ce    => ce,
      sclr  => sclr);   

  add_G : entity work.radd_sub_sclr(rtl)          -- 
    generic map ( 
      width     => OWIDTH+1, 
      add       => true,
      a_signed  => true,
      b_signed  => false,
      delay     => 2-FABRIC_ADDS,
      fabric    => FABRIC_ADDS)   
    port map (
      clk   => clk,
      a     => Bcoef_by_Cr_rnd(MWIDTH-2 downto MWIDTH-OWIDTH-2),
      b     => Y_padded,
      s     => G_int,
      c_in  => logic0,
      ce    => ce,
      sclr  => sclr);   

  add_B : entity work.radd_sub_sclr(rtl)          -- 
    generic map ( 
      width     => OWIDTH+1, 
      add       => true,
      a_signed  => true,
      b_signed  => false,
      delay     => 2-FABRIC_ADDS,
      fabric    => FABRIC_ADDS)   
    port map (
      clk   => clk,
      a     => Dcoef_by_Cb_rnd(MWIDTH-2 downto MWIDTH-OWIDTH-2),
      b     => Y_padded,
      s     => B_int,
      c_in  => logic0,
      ce    => ce,
      sclr  => sclr);   

-----------------------------------------------------
-- clipping and clamping of R,G,B
-----------------------------------------------------
  clip: if (HAS_CLIP=1) generate
    max_R : entity work.max_sat(rtl) -- Add the logic to catch overflow saturation (max)
      generic map (width => OWIDTH+2)   
      port map (
        a     => R_int,  
        max   => MAXvec,
        ma    => R_postmax,
        clk   => clk,
        ce    => ce,
        sclr  => sclr);
  
    max_G : entity work.max_sat(rtl)  -- Add the logic to catch overflow saturation (max)
      generic map (width => OWIDTH+2)   
      port map (
        a     => G_int,  
        max   => MAXvec,
        ma    => G_postmax,
        clk   => clk,
        ce    => ce,
        sclr  => sclr);
  
    max_B : entity work.max_sat(rtl) -- Add the logic to catch overflow saturation (max)
      generic map (width => OWIDTH+2)   
      port map (
        a     => B_int,  
        max   => MAXvec,
        ma    => B_postmax,
        clk   => clk,
        ce    => ce,
        sclr  => sclr);
  end generate;
  
  no_clip: if (HAS_CLIP/=1) generate
    R_postmax <= R_int;
    G_postmax <= G_int;
    B_postmax <= B_int;   
  end generate;

  clamp: if (HAS_CLAMP=1) generate
    min_R : entity work.min_sat(rtl) -- Add the logic to catch underflow saturation (min)
      generic map (width => OWIDTH+2)   
      port map (
        a     => R_postmax,
        min   => MINvec,
        ma    => R_postmin,
        clk   => clk,
        ce    => ce,
        sclr  => sclr);
  
    min_G : entity work.min_sat(rtl)   -- Add the logic to catch underflow saturation (min)
      generic map (width => OWIDTH+2)   
      port map (
        a     => G_postmax,  
        min   => MINvec,
        ma    => G_postmin,
        clk   => clk,
        ce    => ce,
        sclr  => sclr);
  
    min_B : entity work.min_sat(rtl) -- Add the logic to catch underflow saturation (min)
      generic map (width => OWIDTH+2)   
      port map (
        a     => B_postmax,
        min   => MINvec,
        ma    => B_postmin,
        clk   => clk,
        ce    => ce,
        sclr  => sclr);
  end generate;

  no_clamp: if (HAS_CLAMP/=1) generate
    R_postmin <= R_postmax;
    G_postmin <= G_postmax;
    B_postmin <= B_postmax;   
  end generate;
  
  R  <= R_postmin(OWIDTH-1 downto 0);
  G  <= G_postmin(OWIDTH-1 downto 0);
  B  <= B_postmin(OWIDTH-1 downto 0);

end rtl;