xil_ycrcb2rgb.vhd

VHDL代码

  --*******************************************************************
-- Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
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-- Xilinx is providing this design, code, or information
-- "as is" solely for use in developing programs and
-- solutions for Xilinx devices. By providing this design,
-- code, or information as one possible implementation of
-- this feature, application or standard, Xilinx is making no
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--
-- This copyright and support notice must be retained as part
-- of this text at all times. (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
-- Title - Xil_YCrCb2RGB.vhd
-- Author(s) - GZ & WCC, Xilinx
-- Creation - 7 Dec 2005
--
-- $RCSfile: Xil_YCrCb2RGB.vhd,v $ $Revision: 1.10 $ $Date: 2006/03/15 19:56:55 $
--
-- Description -
--
--
-- 
--*******************************************************************

-- ******************************************************************
--  *007*   YCrCb2RGB Macro from imagexlib
--
-- Description: Color Space Converter (YCrCb to RGB)
--
-- ******************************************************************

--LIBRARY genxlib;
--USE genxlib.genxlib_utils.ALL;
--
--LIBRARY mathxlib;
--USE mathxlib.mathxlib_utils.ALL;
--
--LIBRARY imagexlib;
--USE imagexlib.imagexlib_utils.ALL;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all; 

LIBRARY work;
USE work.color_space_pkg.all;

LIBRARY work;
USE work.genxlib_utils.ALL;

-- ******************************************************************
--  *009*   YCrCb2RGB Macro
--
-- Description: Color Space Converter (RGB to YCrCb)
--
-- Generalized conversion:
--
--  R = (Y - Yoffset) + ACoeff' * (Cr - Coffset)                         
--  G = (Y - Yoffset) + BCoeff' * (Cr - 0.5) + CCoeff' * (Cb - 0.5) 
--  B = (Y - Yoffset) + DCoeff' * (Cb - 0.5)     
--
--  R = Y + ACoeff' * Cr                - Roffset                         
--  G = Y + BCoeff' * Cr + CCoeff' * Cb - Goffset 
--  B = Y + DCoeff' * Cb                - Boffset     
--
--  In order to complement RGB2YCrCb:
--  
--  ACoeff' = 1/CCOEFF
--  BCoeff' = ACOEFF/CCOEFF * (1-ACOEFF-BCOEFF)
--  CCoeff' = BCOEFF/DCOEFF * (1-ACOEFF-BCOEFF)
--  DCoeff' = 1/DCOEFF
--  Roffset = Yoffset + Acoeff' * Coffset 
--  Goffset = Yoffset + (Bcoeff' + Ccoeff') * Coffset 
--  Boffset = Yoffset + Dcoeff' * Coffset 
--
-- ITU 601 (SDTV) standard:
-- if RGB data is between 0 and 255 

--  R = Y  + 1.40252 * (Cr - 0.5)                         
--  G = Y  - 0.24642 * (Cr - 0.5) - 0.11840 * (Cb - 0.5) 
--  B = Y  + 1.77305 * (Cb - 0.5)     
--
-- In order to better match the RGB2YCbCr module:
-- For R: ACoeff' = (1/CCOEF) value 2048/1460 is approximated instead of 1.40252
-- For B: DCoeff' = (1/DCOEF) value 2048/1155 is approximated instead of 1.77305
--  

entity Xil_YCrCb2RGB is   
  generic ( 
    FAMILY_HAS_MAC: integer:= 1;
    FABRIC_ADDS   : integer:= 1; -- Adders are implemented using logic fabric based adders
    IWIDTH        : integer:= 9;
    CWIDTH        : integer:= 13; -- Coefficients are signed, CWIDTH.CWIDTH-2 format
    MWIDTH        : integer:= 23; -- ONLY FOR NON-V4: Controls bits witheld after mults. 
    OWIDTH        : integer:= 9;  -- OTHERWISE (default) IWIDTH+CWIDTH+1;
    RGBMAX        : integer:= 255;
    RGBMIN        : integer:= 0;
    ACOEF         : integer:= 2872;   --    1.4023   *pow2(CWIDTH-2) 
    BCOEF         : integer:= -1461;  --    -0.7133  *pow2(CWIDTH-2) 
    CCOEF         : integer:= -703;   --    -0.3434  *pow2(CWIDTH-2) 
    DCOEF         : integer:= 3630;   --    1.7724   *pow2(CWIDTH-2) 
    ROFFSET       : integer:= -366592;  -- Should be MWIDTH bits wide 
    GOFFSET       : integer:= 278016;   
    BOFFSET       : integer:= -463616;
    HAS_CLIP      : integer:= 1; 
    HAS_CLAMP     : integer:= 1);     
  port (                               
    Y             : in std_logic_vector(IWIDTH-1 downto 0);  -- Y  = a(R-G) + G + b(B-G)
    Cr            : in std_logic_vector(IWIDTH-1 downto 0);  -- Cr = d(R-Y)  
    Cb            : in std_logic_vector(IWIDTH-1 downto 0);  -- Cb = c(B-Y)
    R             : out std_logic_vector(OWIDTH-1 downto 0);   
    G             : out std_logic_vector(OWIDTH-1 downto 0);
    B             : out std_logic_vector(OWIDTH-1 downto 0);
    V_SYNC_in     : in std_logic := '0';
    H_SYNC_in     : in std_logic := '0';
    PIX_EN_in     : in std_logic := '1';
    V_SYNC_out    : out std_logic;
    H_SYNC_out    : out std_logic;
    PIX_EN_out    : out std_logic;
    clk           : in std_logic;
    ce            : in std_logic := '1';
    sclr          : in std_logic := '0');
end Xil_YCrCb2RGB;    

architecture rtl of Xil_YCrCb2RGB is            

-- High level constants 
  constant MODULE_LATENCY : integer := YCrCb2RGB_LATENCY(FAMILY_HAS_MAC, FABRIC_ADDS, HAS_CLIP, HAS_CLAMP); -- ADDER_DELAY is set to 1, MULT_DELAY is 2
  constant ACOEFvec       : std_logic_vector(CWIDTH-1 downto 0) := conv_std_logic_vector(ACOEF, CWIDTH); --     ACOEF SRL ACOEFF_RANGE, CWIDTH); -- ACOEFF constant is normalized
  constant BCOEFvec       : std_logic_vector(CWIDTH-1 downto 0) := conv_std_logic_vector(BCOEF, CWIDTH); --     BCOEF SRL BCOEFF_RANGE, CWIDTH); -- BCOEFF constant is normalized
  constant CCOEFvec       : std_logic_vector(CWIDTH-1 downto 0) := conv_std_logic_vector(CCOEF,CWIDTH);
  constant DCOEFvec       : std_logic_vector(CWIDTH-1 downto 0) := conv_std_logic_vector(DCOEF,CWIDTH);
  constant Goffsetvec     : std_logic_vector(MWIDTH-1 downto 0) := conv_std_logic_vector(GOFFSET,MWIDTH);
  constant Roffsetvec     : std_logic_vector(MWIDTH-1 downto 0) := conv_std_logic_vector(ROFFSET,MWIDTH);
  constant Boffsetvec     : std_logic_vector(MWIDTH-1 downto 0) := conv_std_logic_vector(BOFFSET,MWIDTH);
  constant MAXvec         : std_logic_vector(OWIDTH+1 downto 0) := conv_std_logic_vector(RGBMAX,OWIDTH+2);
  constant MINvec         : std_logic_vector(OWIDTH+1 downto 0) := conv_std_logic_vector(RGBMIN,OWIDTH+2);

-- This is the delay of a virtex4 multiplier followed by a rounder. In order to facilitate
-- grouping the rounder with the mult into the same DSP48, overall latency must be 2

-- Low level constants 
  constant logic0         : std_logic := '0';
  constant logic1         : std_logic := '1';

-- signal declarations
  signal Cr_delay         : std_logic_vector(IWIDTH downto 0); 
  signal Cb_delay         : std_logic_vector(IWIDTH downto 0); 
  signal Cb_unsign        : std_logic_vector(IWIDTH downto 0); 
  signal Y_delay          : std_logic_vector(IWIDTH-1 downto 0); 
  signal Y_padded         : std_logic_vector(OWIDTH downto 0); 
  signal Acoef_by_Cr      : std_logic_vector(IWIDTH+CWIDTH   downto 0);
  signal Bcoef_by_Cr      : std_logic_vector(IWIDTH+CWIDTH downto 0);
  signal Ccoef_by_Cb      : std_logic_vector(IWIDTH+CWIDTH downto 0); 
  signal Dcoef_by_Cb      : std_logic_vector(IWIDTH+CWIDTH downto 0);
  signal Acoef_by_Cr_rnd  : std_logic_vector(MWIDTH downto 0); 
  signal Bcoef_by_Cr_rnd  : std_logic_vector(MWIDTH downto 0); 
  signal Ccoef_by_Cb_rnd  : std_logic_vector(MWIDTH downto 0); 
  signal Dcoef_by_Cb_rnd  : std_logic_vector(MWIDTH downto 0); 
  signal G_int            : std_logic_vector(OWIDTH+1 downto 0); 
  signal B_int            : std_logic_vector(OWIDTH+1 downto 0); 
  signal R_int            : std_logic_vector(OWIDTH+1 downto 0); 
  signal G_postmax        : std_logic_vector(OWIDTH+1 downto 0); 
  signal B_postmax        : std_logic_vector(OWIDTH+1 downto 0); 
  signal R_postmax        : std_logic_vector(OWIDTH+1 downto 0); 
  signal G_postmin        : std_logic_vector(OWIDTH+1 downto 0); 
  signal B_postmin        : std_logic_vector(OWIDTH+1 downto 0); 
  signal R_postmin        : std_logic_vector(OWIDTH+1 downto 0); 
  signal sync_in          : std_logic_vector(2 downto 0); 
  signal sync_out         : std_logic_vector(2 downto 0); 

begin        

---------------------------------------------------------------------
--  Generate the output sync signals  
---------------------------------------------------------------------

  SYNC_in(2) <= PIX_EN_in;
  SYNC_in(1) <= V_SYNC_in;
  SYNC_in(0) <= H_SYNC_in;
  
  del_SYNC : entity work.delay(rtl) 
    generic map ( 
      width => 3, 
      delay => MODULE_LATENCY )   
    port map (
      clk   => clk,
      d     => SYNC_in,  
      q     => SYNC_out,
      ce    => ce);

  PIX_EN_out <= SYNC_out(2);
  V_SYNC_out <= SYNC_out(1);
  H_SYNC_out <= SYNC_out(0);

--------------------------------------------------------------------
-- Create and round Cb*BCOEFF, Cb*DCOEFF, Cr*ACOEFF, Cr*CCOEFF
--------------------------------------------------------------------
  
  del_Cr : entity work.delay(rtl)   -- Delay Cr, so Acoef_by_Cr arrives in sync 
    generic map (                   -- with Ccoef_by_Cb to the adder/rounder 
      width => IWIDTH, 
      delay => 1)   
    port map (
      clk   => clk,
      d     => Cr,  
      q     => Cr_delay(IWIDTH-1 downto 0),
      ce    => ce);

  del_Cb : entity work.delay(rtl)   -- Delay Cb, so Dcoef_by_Cb arrives in sync 
    generic map (                   -- with B_int and G_int are in sync.
      width => IWIDTH, 
      delay => 1)   
    port map (
      clk   => clk,
      d     => Cb,  
      q     => Cb_delay(IWIDTH-1 downto 0),
      ce    => ce);

  Cb_unsign(IWIDTH-1 downto 0) <= Cb;
  Cb_unsign(IWIDTH) <= '0';       -- Making sure that Cb and Cr signals are 
  Cb_delay(IWIDTH) <= '0';        -- interpreted as unsigned 
  Cr_delay(IWIDTH) <= '0';        -- at the mutlipliers
  
  sp3_v2_v2p: if (FAMILY_HAS_MAC=0) generate
    mult_aCr: entity work.mult(rtl)              -- ACOEFF * Cr
      generic map ( 
        IWIDTHA => IWIDTH+1, 
        IWIDTHB => CWIDTH)   
      port map (
        clk     => clk,
        ce      => ce,
        sclr    => sclr,
        a       => Cr_delay,
        b       => ACOEFvec,
        p       => Acoef_by_Cr);

    mult_bCr: entity work.mult(rtl)              -- BCOEFF * Cr
      generic map ( 
        IWIDTHA => IWIDTH+1, 
        IWIDTHB => CWIDTH)   
      port map (
        clk     => clk,
        ce      => ce,
        sclr    => sclr,
        a       => Cr_delay,
        b       => BCOEFvec,
        p       => Bcoef_by_Cr);

    mult_cCb: entity work.mult(rtl)              -- CCOEFF * Cb
      generic map ( 
        IWIDTHA => IWIDTH+1, 
        IWIDTHB => CWIDTH)   
      port map (
        clk     => clk,
        ce      => ce,
        sclr    => sclr,
        a       => Cb_unsign,
        b       => CCOEFvec,
        p       => Ccoef_by_Cb);

    mult_dCb: entity work.mult(rtl)              -- DCOEFF * Cb
      generic map ( 
        IWIDTHA => IWIDTH+1, 
        IWIDTHB => CWIDTH)   
      port map (
        clk     => clk,
        ce      => ce,
        sclr    => sclr,
        a       => Cb_delay,
        b       => DCOEFvec,
        p       => Dcoef_by_Cb);
        

    round_aCr : entity work.radd_sub_sclr(rtl)   -- Rounding and offset compensating R with one adder
      generic map ( 
        width => MWIDTH, 
        add   => true,