loopback.par

Xilinx的培训教程的源码 virtex

Release 8.2.01i par I.32
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

XCOJEFFW30::  Wed Aug 16 12:37:03 2006

par -w loopback.ncd loopback loopback.pcf 


Constraints file: loopback.pcf.
Loading device for application Rf_Device from file '2vp30.nph' in environment c:\Xilinx\ISE82.
   "loopback" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.400 Volts. (default - Range: 1.400 to 1.600 Volts)


Device speed data version:  "PRODUCTION 1.92 2006-06-02".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 16     12%
   Number of DCMs                      1 out of 8      12%
   Number of External IOBs            21 out of 556     3%
      Number of LOCed IOBs            12 out of 21     57%

   Number of RAMB16s                   1 out of 136     1%
   Number of SLICEs                  157 out of 13696   1%


Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989db7) REAL time: 6 secs 

Phase 2.7
WARNING:Place:837 - Partially locked IO Bus is found. 
    Following components of the bus are not locked: 
   	 Comp: switches<7>
   	 Comp: switches<6>
   	 Comp: switches<5>
   	 Comp: switches<4>

WARNING:Place:837 - Partially locked IO Bus is found. 
    Following components of the bus are not locked: 
   	 Comp: leds<7>
   	 Comp: leds<6>
   	 Comp: leds<5>
   	 Comp: leds<4>

INFO:Place:834 - Only a subset of IOs are locked. Out of 21 IOs, 12 are locked and 9 are not locked. If you would like
   to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 2 (or more). 
Phase 2.7 (Checksum:1312cfe) REAL time: 6 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 6 secs 

Phase 4.2
.


Phase 4.2 (Checksum:26259fc) REAL time: 11 secs 

Phase 5.30
Phase 5.30 (Checksum:2faf07b) REAL time: 11 secs 

Phase 6.3
Phase 6.3 (Checksum:39386fa) REAL time: 11 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 11 secs 

Phase 8.8
.........................................................................................................................................................................
....
................................................................................................
......
......
......
Phase 8.8 (Checksum:9ce22f) REAL time: 13 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 13 secs 

Phase 10.18
Phase 10.18 (Checksum:5f5e0f6) REAL time: 14 secs 

Phase 11.5
Phase 11.5 (Checksum:68e7775) REAL time: 14 secs 

Phase 12.27
Phase 12.27 (Checksum:7270df4) REAL time: 14 secs 

Phase 13.24
Phase 13.24 (Checksum:7bfa473) REAL time: 14 secs 

Writing design to file loopback.ncd


Total REAL time to Placer completion: 15 secs 
Total CPU time to Placer completion: 13 secs 

Starting Router

Phase 1: 1705 unrouted;       REAL time: 26 secs 

Phase 2: 1487 unrouted;       REAL time: 27 secs 

Phase 3: 291 unrouted;       REAL time: 27 secs 

Phase 4: 291 unrouted; (0)      REAL time: 28 secs 

Phase 5: 291 unrouted; (0)      REAL time: 28 secs 

Phase 6: 291 unrouted; (0)      REAL time: 28 secs 

Phase 7: 0 unrouted; (0)      REAL time: 28 secs 

Phase 8: 0 unrouted; (0)      REAL time: 28 secs 


Total REAL time to Router completion: 28 secs 
Total CPU time to Router completion: 27 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|            clk50MHz |     BUFGMUX0P| No   |  122 |  0.052     |  1.257      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.660
   The MAXIMUM PIN DELAY IS:                               2.705
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.730

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
        1399         391          12           0           0           0

Timing Score: 0

Number of Timing Constraints that were not applied: 1

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of
                                            |            |            | Levels | Slack      |errors   
------------------------------------------------------------------------------------------------------
  OFFSET = IN 6 ns BEFORE COMP "clk"        | 6.000ns    | 4.826ns    | 1      | 1.174ns    | 0       
------------------------------------------------------------------------------------------------------
  OFFSET = OUT 7.5 ns AFTER COMP "clk"      | 7.500ns    | 4.274ns    | 1      | 3.226ns    | 0       
------------------------------------------------------------------------------------------------------
  TS_Inst_my_dcm_CLKFX_BUF = PERIOD TIMEGRP | 40.000ns   | 6.714ns    | 6      | 33.286ns   | 0       
   "Inst_my_dcm_CLKFX_BUF" TS_clk / 0.5     |            |            |        |            |         
       HIGH 50%                             |            |            |        |            |         
------------------------------------------------------------------------------------------------------
  TS_clk = PERIOD TIMEGRP "clk" 20 ns HIGH  | N/A        | N/A        | N/A    | N/A        | N/A     
  50%                                       |            |            |        |            |         
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 31 secs 
Total CPU time to PAR completion: 29 secs 

Peak Memory Usage:  233 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 2
Number of info messages: 1

Writing design to file loopback.ncd



PAR done!