📄 loopback.pcf
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//! **************************************************************************
// Written by: Map I.32 on Wed Aug 16 12:36:10 2006
//! **************************************************************************
SCHEMATIC START;
COMP "rs232_rx" LOCATE = SITE "AJ8" LEVEL 1;
COMP "rs232_tx" LOCATE = SITE "AE7" LEVEL 1;
COMP "clk" LOCATE = SITE "AJ15" LEVEL 1;
COMP "rst" LOCATE = SITE "AG5" LEVEL 1;
COMP "switches<0>" LOCATE = SITE "AC11" LEVEL 1;
COMP "switches<1>" LOCATE = SITE "AD11" LEVEL 1;
COMP "switches<2>" LOCATE = SITE "AF8" LEVEL 1;
COMP "switches<3>" LOCATE = SITE "AF9" LEVEL 1;
COMP "leds<0>" LOCATE = SITE "AC4" LEVEL 1;
COMP "leds<1>" LOCATE = SITE "AC3" LEVEL 1;
COMP "leds<2>" LOCATE = SITE "AA6" LEVEL 1;
COMP "leds<3>" LOCATE = SITE "AA5" LEVEL 1;
TIMEGRP Inst_my_dcm_CLKFX_BUF = BEL "in_port_0" BEL "in_port_1" BEL
"in_port_2" BEL "in_port_3" BEL "in_port_4" BEL "in_port_5" BEL
"in_port_6" BEL "in_port_7" BEL "en_16_x_baud" BEL "leds_0" BEL
"leds_1" BEL "leds_2" BEL "leds_3" BEL "leds_4" BEL "leds_5" BEL
"leds_6" BEL "leds_7" BEL "read_from_uart" BEL "baud_count_0" BEL
"baud_count_1" BEL "baud_count_2" BEL "baud_count_3" BEL
"baud_count_4" BEL "baud_count_5" BEL "baud_count_6" BEL
"baud_count_7" BEL "baud_count_8" BEL "my_program/ram_1024_x_18.A" BEL
"my_kcpsm3/toggle_flop" BEL "my_kcpsm3/reset_flop1" BEL
"my_kcpsm3/reset_flop2" BEL "my_kcpsm3/flag_write_flop" BEL
"my_kcpsm3/zero_flag_flop" BEL "my_kcpsm3/carry_flag_flop" BEL
"my_kcpsm3/pc_loop[0].register_bit" BEL
"my_kcpsm3/pc_loop[1].register_bit" BEL
"my_kcpsm3/pc_loop[2].register_bit" BEL
"my_kcpsm3/pc_loop[3].register_bit" BEL
"my_kcpsm3/pc_loop[4].register_bit" BEL
"my_kcpsm3/pc_loop[5].register_bit" BEL
"my_kcpsm3/pc_loop[6].register_bit" BEL
"my_kcpsm3/pc_loop[7].register_bit" BEL
"my_kcpsm3/pc_loop[8].register_bit" BEL
"my_kcpsm3/pc_loop[9].register_bit" BEL
"my_kcpsm3/register_write_flop" BEL "my_kcpsm3/memory_write_flop" BEL
"my_kcpsm3/store_loop[0].store_flop" BEL
"my_kcpsm3/store_loop[1].store_flop" BEL
"my_kcpsm3/store_loop[2].store_flop" BEL
"my_kcpsm3/store_loop[3].store_flop" BEL
"my_kcpsm3/store_loop[4].store_flop" BEL
"my_kcpsm3/store_loop[5].store_flop" BEL
"my_kcpsm3/store_loop[6].store_flop" BEL
"my_kcpsm3/store_loop[7].store_flop" BEL
"my_kcpsm3/logical_loop[0].logical_flop" BEL
"my_kcpsm3/logical_loop[1].logical_flop" BEL
"my_kcpsm3/logical_loop[2].logical_flop" BEL
"my_kcpsm3/logical_loop[3].logical_flop" BEL
"my_kcpsm3/logical_loop[4].logical_flop" BEL
"my_kcpsm3/logical_loop[5].logical_flop" BEL
"my_kcpsm3/logical_loop[6].logical_flop" BEL
"my_kcpsm3/logical_loop[7].logical_flop" BEL "my_kcpsm3/pipeline_bit"
BEL "my_kcpsm3/shift_loop[0].shift_flop" BEL
"my_kcpsm3/shift_loop[1].shift_flop" BEL
"my_kcpsm3/shift_loop[2].shift_flop" BEL
"my_kcpsm3/shift_loop[3].shift_flop" BEL
"my_kcpsm3/shift_loop[4].shift_flop" BEL
"my_kcpsm3/shift_loop[5].shift_flop" BEL
"my_kcpsm3/shift_loop[6].shift_flop" BEL
"my_kcpsm3/shift_loop[7].shift_flop" BEL
"my_kcpsm3/arith_loop[0].arith_flop" BEL
"my_kcpsm3/arith_loop[1].arith_flop" BEL
"my_kcpsm3/arith_loop[2].arith_flop" BEL
"my_kcpsm3/arith_loop[3].arith_flop" BEL
"my_kcpsm3/arith_loop[4].arith_flop" BEL
"my_kcpsm3/arith_loop[5].arith_flop" BEL
"my_kcpsm3/arith_loop[6].arith_flop" BEL
"my_kcpsm3/arith_loop[7].msb_arith.arith_carry_flop" BEL
"my_kcpsm3/arith_loop[7].arith_flop" BEL "my_kcpsm3/sel_group_flop"
BEL "my_kcpsm3/write_strobe_flop" BEL "my_kcpsm3/read_strobe_flop" BEL
"my_kcpsm3/stack_ram_loop[0].stack_flop" BEL
"my_kcpsm3/stack_ram_loop[1].stack_flop" BEL
"my_kcpsm3/stack_ram_loop[2].stack_flop" BEL
"my_kcpsm3/stack_ram_loop[3].stack_flop" BEL
"my_kcpsm3/stack_ram_loop[4].stack_flop" BEL
"my_kcpsm3/stack_ram_loop[5].stack_flop" BEL
"my_kcpsm3/stack_ram_loop[6].stack_flop" BEL
"my_kcpsm3/stack_ram_loop[7].stack_flop" BEL
"my_kcpsm3/stack_ram_loop[8].stack_flop" BEL
"my_kcpsm3/stack_ram_loop[9].stack_flop" BEL
"my_kcpsm3/stack_count_loop[0].register_bit" BEL
"my_kcpsm3/stack_count_loop[1].register_bit" BEL
"my_kcpsm3/stack_count_loop[2].register_bit" BEL
"my_kcpsm3/stack_count_loop[3].register_bit" BEL
"my_kcpsm3/stack_count_loop[4].register_bit" BEL
"receive/buf/count_width_loop[0].register_bit" BEL
"receive/buf/count_width_loop[1].register_bit" BEL
"receive/buf/count_width_loop[2].register_bit" BEL
"receive/buf/count_width_loop[3].register_bit" BEL
"receive/buf/dp_flop" BEL "receive/buf/data_width_loop[0].data_srl"
BEL "receive/buf/data_width_loop[1].data_srl" BEL
"receive/buf/data_width_loop[2].data_srl" BEL
"receive/buf/data_width_loop[3].data_srl" BEL
"receive/buf/data_width_loop[4].data_srl" BEL
"receive/buf/data_width_loop[5].data_srl" BEL
"receive/buf/data_width_loop[6].data_srl" BEL
"receive/buf/data_width_loop[7].data_srl" BEL
"transmit/buf/count_width_loop[0].register_bit" BEL
"transmit/buf/count_width_loop[1].register_bit" BEL
"transmit/buf/count_width_loop[2].register_bit" BEL
"transmit/buf/count_width_loop[3].register_bit" BEL
"transmit/buf/dp_flop" BEL "transmit/buf/data_width_loop[0].data_srl"
BEL "transmit/buf/data_width_loop[1].data_srl" BEL
"transmit/buf/data_width_loop[2].data_srl" BEL
"transmit/buf/data_width_loop[3].data_srl" BEL
"transmit/buf/data_width_loop[4].data_srl" BEL
"transmit/buf/data_width_loop[5].data_srl" BEL
"transmit/buf/data_width_loop[6].data_srl" BEL
"transmit/buf/data_width_loop[7].data_srl" BEL
"receive/kcuart/sync_reg" BEL "receive/kcuart/stop_reg" BEL
"receive/kcuart/data_loop[0].data_reg" BEL
"receive/kcuart/data_loop[1].data_reg" BEL
"receive/kcuart/data_loop[2].data_reg" BEL
"receive/kcuart/data_loop[3].data_reg" BEL
"receive/kcuart/data_loop[4].data_reg" BEL
"receive/kcuart/data_loop[5].data_reg" BEL
"receive/kcuart/data_loop[6].data_reg" BEL
"receive/kcuart/data_loop[7].data_reg" BEL "receive/kcuart/start_reg"
BEL "receive/kcuart/edge_reg" BEL "receive/kcuart/valid_reg" BEL
"receive/kcuart/purge_reg" BEL "receive/kcuart/valid_loop[0].data_reg"
BEL "receive/kcuart/valid_loop[1].data_reg" BEL
"receive/kcuart/valid_loop[2].data_reg" BEL
"receive/kcuart/valid_loop[3].data_reg" BEL
"receive/kcuart/valid_loop[4].data_reg" BEL
"receive/kcuart/valid_loop[5].data_reg" BEL
"receive/kcuart/valid_loop[6].data_reg" BEL
"receive/kcuart/valid_loop[7].data_reg" BEL
"receive/kcuart/valid_loop[8].data_reg" BEL
"receive/kcuart/strobe_reg" BEL
"receive/kcuart/data_loop[0].lsbs.delay15_srl" BEL
"receive/kcuart/data_loop[1].lsbs.delay15_srl" BEL
"receive/kcuart/data_loop[2].lsbs.delay15_srl" BEL
"receive/kcuart/data_loop[3].lsbs.delay15_srl" BEL
"receive/kcuart/data_loop[4].lsbs.delay15_srl" BEL
"receive/kcuart/data_loop[5].lsbs.delay15_srl" BEL
"receive/kcuart/data_loop[6].lsbs.delay15_srl" BEL
"receive/kcuart/data_loop[7].msb.delay15_srl" BEL
"receive/kcuart/start_srl" BEL "receive/kcuart/edge_srl" BEL
"receive/kcuart/valid_loop[0].lsb.delay15_srl" BEL
"receive/kcuart/valid_loop[1].msbs.delay16_srl" BEL
"receive/kcuart/valid_loop[2].msbs.delay16_srl" BEL
"receive/kcuart/valid_loop[3].msbs.delay16_srl" BEL
"receive/kcuart/valid_loop[4].msbs.delay16_srl" BEL
"receive/kcuart/valid_loop[5].msbs.delay16_srl" BEL
"receive/kcuart/valid_loop[6].msbs.delay16_srl" BEL
"receive/kcuart/valid_loop[7].msbs.delay16_srl" BEL
"receive/kcuart/valid_loop[8].msbs.delay16_srl" BEL
"transmit/kcuart/pipeline_serial" BEL
"transmit/kcuart/count_width_loop[0].register_bit" BEL
"transmit/kcuart/count_width_loop[1].register_bit" BEL
"transmit/kcuart/count_width_loop[2].register_bit" BEL
"transmit/kcuart/Tx_start_reg" BEL "transmit/kcuart/Tx_run_reg" BEL
"transmit/kcuart/hot_state_reg" BEL "transmit/kcuart/Tx_bit_reg" BEL
"transmit/kcuart/Tx_stop_reg" BEL "transmit/kcuart/Tx_complete_reg"
BEL "transmit/kcuart/delay14_srl" BEL
"my_kcpsm3/reg_loop[0].register_bit/SP" BEL
"my_kcpsm3/reg_loop[0].register_bit/DP" BEL
"my_kcpsm3/reg_loop[1].register_bit/SP" BEL
"my_kcpsm3/reg_loop[1].register_bit/DP" BEL
"my_kcpsm3/reg_loop[2].register_bit/SP" BEL
"my_kcpsm3/reg_loop[2].register_bit/DP" BEL
"my_kcpsm3/reg_loop[3].register_bit/SP" BEL
"my_kcpsm3/reg_loop[3].register_bit/DP" BEL
"my_kcpsm3/reg_loop[4].register_bit/SP" BEL
"my_kcpsm3/reg_loop[4].register_bit/DP" BEL
"my_kcpsm3/reg_loop[5].register_bit/SP" BEL
"my_kcpsm3/reg_loop[5].register_bit/DP" BEL
"my_kcpsm3/reg_loop[6].register_bit/SP" BEL
"my_kcpsm3/reg_loop[6].register_bit/DP" BEL
"my_kcpsm3/reg_loop[7].register_bit/SP" BEL
"my_kcpsm3/reg_loop[7].register_bit/DP" BEL
"my_kcpsm3/store_loop[0].memory_bit/G.S0" BEL
"my_kcpsm3/store_loop[0].memory_bit/F.S0" BEL
"my_kcpsm3/store_loop[0].memory_bit/F.S1" BEL
"my_kcpsm3/store_loop[0].memory_bit/G.S1" BEL
"my_kcpsm3/store_loop[1].memory_bit/G.S0" BEL
"my_kcpsm3/store_loop[1].memory_bit/F.S0" BEL
"my_kcpsm3/store_loop[1].memory_bit/F.S1" BEL
"my_kcpsm3/store_loop[1].memory_bit/G.S1" BEL
"my_kcpsm3/store_loop[2].memory_bit/G.S0" BEL
"my_kcpsm3/store_loop[2].memory_bit/F.S0" BEL
"my_kcpsm3/store_loop[2].memory_bit/F.S1" BEL
"my_kcpsm3/store_loop[2].memory_bit/G.S1" BEL
"my_kcpsm3/store_loop[3].memory_bit/G.S0" BEL
"my_kcpsm3/store_loop[3].memory_bit/F.S0" BEL
"my_kcpsm3/store_loop[3].memory_bit/F.S1" BEL
"my_kcpsm3/store_loop[3].memory_bit/G.S1" BEL
"my_kcpsm3/store_loop[4].memory_bit/G.S0" BEL
"my_kcpsm3/store_loop[4].memory_bit/F.S0" BEL
"my_kcpsm3/store_loop[4].memory_bit/F.S1" BEL
"my_kcpsm3/store_loop[4].memory_bit/G.S1" BEL
"my_kcpsm3/store_loop[5].memory_bit/G.S0" BEL
"my_kcpsm3/store_loop[5].memory_bit/F.S0" BEL
"my_kcpsm3/store_loop[5].memory_bit/F.S1" BEL
"my_kcpsm3/store_loop[5].memory_bit/G.S1" BEL
"my_kcpsm3/store_loop[6].memory_bit/G.S0" BEL
"my_kcpsm3/store_loop[6].memory_bit/F.S0" BEL
"my_kcpsm3/store_loop[6].memory_bit/F.S1" BEL
"my_kcpsm3/store_loop[6].memory_bit/G.S1" BEL
"my_kcpsm3/store_loop[7].memory_bit/G.S0" BEL
"my_kcpsm3/store_loop[7].memory_bit/F.S0" BEL
"my_kcpsm3/store_loop[7].memory_bit/F.S1" BEL
"my_kcpsm3/store_loop[7].memory_bit/G.S1" BEL
"my_kcpsm3/stack_ram_loop[0].stack_bit/G" BEL
"my_kcpsm3/stack_ram_loop[0].stack_bit/F" BEL
"my_kcpsm3/stack_ram_loop[1].stack_bit/G" BEL
"my_kcpsm3/stack_ram_loop[1].stack_bit/F" BEL
"my_kcpsm3/stack_ram_loop[2].stack_bit/G" BEL
"my_kcpsm3/stack_ram_loop[2].stack_bit/F" BEL
"my_kcpsm3/stack_ram_loop[3].stack_bit/G" BEL
"my_kcpsm3/stack_ram_loop[3].stack_bit/F" BEL
"my_kcpsm3/stack_ram_loop[4].stack_bit/G" BEL
"my_kcpsm3/stack_ram_loop[4].stack_bit/F" BEL
"my_kcpsm3/stack_ram_loop[5].stack_bit/G" BEL
"my_kcpsm3/stack_ram_loop[5].stack_bit/F" BEL
"my_kcpsm3/stack_ram_loop[6].stack_bit/G" BEL
"my_kcpsm3/stack_ram_loop[6].stack_bit/F" BEL
"my_kcpsm3/stack_ram_loop[7].stack_bit/G" BEL
"my_kcpsm3/stack_ram_loop[7].stack_bit/F" BEL
"my_kcpsm3/stack_ram_loop[8].stack_bit/G" BEL
"my_kcpsm3/stack_ram_loop[8].stack_bit/F" BEL
"my_kcpsm3/stack_ram_loop[9].stack_bit/G" BEL
"my_kcpsm3/stack_ram_loop[9].stack_bit/F";
PIN Inst_my_dcm/DCM_INST_pins<20> = BEL "Inst_my_dcm/DCM_INST" PINNAME CLKIN;
TIMEGRP clk = PIN "Inst_my_dcm/DCM_INST_pins<20>";
TS_clk = PERIOD TIMEGRP "clk" 20 ns HIGH 50%;
TS_Inst_my_dcm_CLKFX_BUF = PERIOD TIMEGRP "Inst_my_dcm_CLKFX_BUF" TS_clk / 0.5
HIGH 50%;
OFFSET = IN 6 ns BEFORE COMP "clk";
OFFSET = OUT 7.5 ns AFTER COMP "clk";
SCHEMATIC END;
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