uart_clock.ucf

Xilinx的培训教程的源码 virtex

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "alarm"  LOC = "AC3"  ;
NET "clk"  LOC = "AJ15"  ;
NET "lock"  LOC = "AC4"  ;
NET "rx"  LOC = "AJ8"  ;
NET "tx"  LOC = "AE7"  ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE