loopback.ucf

Xilinx的培训教程的源码 virtex

NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50 %;
OFFSET = IN 6 ns BEFORE "clk"  ;
OFFSET = OUT 7.5 ns AFTER "clk"  ;
#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "clk"  LOC = "AJ15"  ;
NET "leds<0>"  LOC = "AC4"  ;
NET "leds<1>"  LOC = "AC3"  ;
NET "leds<2>"  LOC = "AA6"  ;
NET "leds<3>"  LOC = "AA5"  ;
NET "rs232_rx"  LOC = "AJ8"  ;
NET "rs232_tx"  LOC = "AE7"  ;
NET "rst"  LOC = "AG5"  ;
NET "switches<0>"  LOC = "AC11"  ;
NET "switches<1>"  LOC = "AD11"  ;
NET "switches<2>"  LOC = "AF8"  ;
NET "switches<3>"  LOC = "AF9"  ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE