loopback.pcf

Xilinx的培训教程的源码 virtex

//! **************************************************************************
// Written by: Map I.32 on Wed Aug 16 11:32:50 2006
//! **************************************************************************

SCHEMATIC START;
COMP "leds<0>" LOCATE = SITE "AC4" LEVEL 1;
COMP "leds<1>" LOCATE = SITE "AC3" LEVEL 1;
COMP "leds<2>" LOCATE = SITE "AA6" LEVEL 1;
COMP "leds<3>" LOCATE = SITE "AA5" LEVEL 1;
COMP "rs232_rx" LOCATE = SITE "AJ8" LEVEL 1;
COMP "rs232_tx" LOCATE = SITE "AE7" LEVEL 1;
COMP "clk" LOCATE = SITE "AJ15" LEVEL 1;
COMP "rst" LOCATE = SITE "AG5" LEVEL 1;
COMP "switches<0>" LOCATE = SITE "AC11" LEVEL 1;
COMP "switches<1>" LOCATE = SITE "AD11" LEVEL 1;
COMP "switches<2>" LOCATE = SITE "AF8" LEVEL 1;
COMP "switches<3>" LOCATE = SITE "AF9" LEVEL 1;
TIMEGRP instance_name_CLKFX_BUF = BEL "en_16_x_baud" BEL "in_port_0" BEL
        "in_port_1" BEL "in_port_2" BEL "in_port_3" BEL "in_port_4" BEL
        "in_port_5" BEL "in_port_6" BEL "in_port_7" BEL "read_from_uart" BEL
        "leds_0" BEL "leds_1" BEL "leds_2" BEL "leds_3" BEL "leds_4" BEL
        "leds_5" BEL "leds_6" BEL "leds_7" BEL "baud_count_0" BEL
        "baud_count_1" BEL "baud_count_2" BEL "baud_count_3" BEL
        "baud_count_4" BEL "baud_count_5" BEL "baud_count_6" BEL
        "baud_count_7" BEL "baud_count_8" BEL "my_program/ram_1024_x_18.A" BEL
        "my_kcpsm3/toggle_flop" BEL "my_kcpsm3/reset_flop1" BEL
        "my_kcpsm3/reset_flop2" BEL "my_kcpsm3/flag_write_flop" BEL
        "my_kcpsm3/zero_flag_flop" BEL "my_kcpsm3/carry_flag_flop" BEL
        "my_kcpsm3/pc_loop_register_bit_0" BEL
        "my_kcpsm3/pc_loop_register_bit_1" BEL
        "my_kcpsm3/pc_loop_register_bit_2" BEL
        "my_kcpsm3/pc_loop_register_bit_3" BEL
        "my_kcpsm3/pc_loop_register_bit_4" BEL
        "my_kcpsm3/pc_loop_register_bit_5" BEL
        "my_kcpsm3/pc_loop_register_bit_6" BEL
        "my_kcpsm3/pc_loop_register_bit_7" BEL
        "my_kcpsm3/pc_loop_register_bit_8" BEL
        "my_kcpsm3/pc_loop_register_bit_9" BEL "my_kcpsm3/register_write_flop"
        BEL "my_kcpsm3/memory_write_flop" BEL "my_kcpsm3/store_flop_0" BEL
        "my_kcpsm3/store_flop_1" BEL "my_kcpsm3/store_flop_2" BEL
        "my_kcpsm3/store_flop_3" BEL "my_kcpsm3/store_flop_4" BEL
        "my_kcpsm3/store_flop_5" BEL "my_kcpsm3/store_flop_6" BEL
        "my_kcpsm3/store_flop_7" BEL "my_kcpsm3/logical_flop_0" BEL
        "my_kcpsm3/logical_flop_1" BEL "my_kcpsm3/logical_flop_2" BEL
        "my_kcpsm3/logical_flop_3" BEL "my_kcpsm3/logical_flop_4" BEL
        "my_kcpsm3/logical_flop_5" BEL "my_kcpsm3/logical_flop_6" BEL
        "my_kcpsm3/logical_flop_7" BEL "my_kcpsm3/pipeline_bit" BEL
        "my_kcpsm3/shift_flop_0" BEL "my_kcpsm3/shift_flop_1" BEL
        "my_kcpsm3/shift_flop_2" BEL "my_kcpsm3/shift_flop_3" BEL
        "my_kcpsm3/shift_flop_4" BEL "my_kcpsm3/shift_flop_5" BEL
        "my_kcpsm3/shift_flop_6" BEL "my_kcpsm3/shift_flop_7" BEL
        "my_kcpsm3/arith_flop_0" BEL "my_kcpsm3/arith_flop_1" BEL
        "my_kcpsm3/arith_flop_2" BEL "my_kcpsm3/arith_flop_3" BEL
        "my_kcpsm3/arith_flop_4" BEL "my_kcpsm3/arith_flop_5" BEL
        "my_kcpsm3/arith_flop_6" BEL "my_kcpsm3/arith_flop_7" BEL
        "my_kcpsm3/arith_carry_flop" BEL "my_kcpsm3/sel_group_flop" BEL
        "my_kcpsm3/write_strobe_flop" BEL "my_kcpsm3/read_strobe_flop" BEL
        "my_kcpsm3/stack_flop_0" BEL "my_kcpsm3/stack_flop_1" BEL
        "my_kcpsm3/stack_flop_2" BEL "my_kcpsm3/stack_flop_3" BEL
        "my_kcpsm3/stack_flop_4" BEL "my_kcpsm3/stack_flop_5" BEL
        "my_kcpsm3/stack_flop_6" BEL "my_kcpsm3/stack_flop_7" BEL
        "my_kcpsm3/stack_flop_8" BEL "my_kcpsm3/stack_flop_9" BEL
        "my_kcpsm3/stack_count_loop_register_bit_0" BEL
        "my_kcpsm3/stack_count_loop_register_bit_1" BEL
        "my_kcpsm3/stack_count_loop_register_bit_2" BEL
        "my_kcpsm3/stack_count_loop_register_bit_3" BEL
        "my_kcpsm3/stack_count_loop_register_bit_4" BEL
        "receive/buf_0/register_bit_0" BEL "receive/buf_0/register_bit_1" BEL
        "receive/buf_0/register_bit_2" BEL "receive/buf_0/register_bit_3" BEL
        "receive/buf_0/dp_flop" BEL "receive/buf_0/data_srl_0" BEL
        "receive/buf_0/data_srl_1" BEL "receive/buf_0/data_srl_2" BEL
        "receive/buf_0/data_srl_3" BEL "receive/buf_0/data_srl_4" BEL
        "receive/buf_0/data_srl_5" BEL "receive/buf_0/data_srl_6" BEL
        "receive/buf_0/data_srl_7" BEL "transmit/buf_0/register_bit_0" BEL
        "transmit/buf_0/register_bit_1" BEL "transmit/buf_0/register_bit_2"
        BEL "transmit/buf_0/register_bit_3" BEL "transmit/buf_0/dp_flop" BEL
        "transmit/buf_0/data_srl_0" BEL "transmit/buf_0/data_srl_1" BEL
        "transmit/buf_0/data_srl_2" BEL "transmit/buf_0/data_srl_3" BEL
        "transmit/buf_0/data_srl_4" BEL "transmit/buf_0/data_srl_5" BEL
        "transmit/buf_0/data_srl_6" BEL "transmit/buf_0/data_srl_7" BEL
        "receive/kcuart/sync_reg" BEL "receive/kcuart/stop_reg" BEL
        "receive/kcuart/data_reg_0" BEL "receive/kcuart/data_reg_1" BEL
        "receive/kcuart/data_reg_2" BEL "receive/kcuart/data_reg_3" BEL
        "receive/kcuart/data_reg_4" BEL "receive/kcuart/data_reg_5" BEL
        "receive/kcuart/data_reg_6" BEL "receive/kcuart/data_reg_7" BEL
        "receive/kcuart/start_reg" BEL "receive/kcuart/edge_reg" BEL
        "receive/kcuart/valid_reg" BEL "receive/kcuart/purge_reg" BEL
        "receive/kcuart/valid_data_reg_0" BEL
        "receive/kcuart/valid_data_reg_1" BEL
        "receive/kcuart/valid_data_reg_2" BEL
        "receive/kcuart/valid_data_reg_3" BEL
        "receive/kcuart/valid_data_reg_4" BEL
        "receive/kcuart/valid_data_reg_5" BEL
        "receive/kcuart/valid_data_reg_6" BEL
        "receive/kcuart/valid_data_reg_7" BEL
        "receive/kcuart/valid_data_reg_8" BEL "receive/kcuart/strobe_reg" BEL
        "receive/kcuart/delay15_srl_0" BEL "receive/kcuart/delay15_srl_1" BEL
        "receive/kcuart/delay15_srl_2" BEL "receive/kcuart/delay15_srl_3" BEL
        "receive/kcuart/delay15_srl_4" BEL "receive/kcuart/delay15_srl_5" BEL
        "receive/kcuart/delay15_srl_6" BEL "receive/kcuart/delay15_srl_7" BEL
        "receive/kcuart/start_srl" BEL "receive/kcuart/edge_srl" BEL
        "receive/kcuart/valid_delay15_srl_0" BEL
        "receive/kcuart/valid_delay16_srl_1" BEL
        "receive/kcuart/valid_delay16_srl_2" BEL
        "receive/kcuart/valid_delay16_srl_3" BEL
        "receive/kcuart/valid_delay16_srl_4" BEL
        "receive/kcuart/valid_delay16_srl_5" BEL
        "receive/kcuart/valid_delay16_srl_6" BEL
        "receive/kcuart/valid_delay16_srl_7" BEL
        "receive/kcuart/valid_delay16_srl_8" BEL
        "transmit/kcuart/pipeline_serial" BEL "transmit/kcuart/register_bit_0"
        BEL "transmit/kcuart/register_bit_1" BEL
        "transmit/kcuart/register_bit_2" BEL "transmit/kcuart/Tx_start_reg"
        BEL "transmit/kcuart/Tx_run_reg" BEL "transmit/kcuart/hot_state_reg"
        BEL "transmit/kcuart/Tx_bit_reg" BEL "transmit/kcuart/Tx_stop_reg" BEL
        "transmit/kcuart/Tx_complete_reg" BEL "transmit/kcuart/delay14_srl"
        BEL "my_kcpsm3/reg_loop_register_bit_0/SP" BEL
        "my_kcpsm3/reg_loop_register_bit_0/DP" BEL
        "my_kcpsm3/reg_loop_register_bit_1/SP" BEL
        "my_kcpsm3/reg_loop_register_bit_1/DP" BEL
        "my_kcpsm3/reg_loop_register_bit_2/SP" BEL
        "my_kcpsm3/reg_loop_register_bit_2/DP" BEL
        "my_kcpsm3/reg_loop_register_bit_3/SP" BEL
        "my_kcpsm3/reg_loop_register_bit_3/DP" BEL
        "my_kcpsm3/reg_loop_register_bit_4/SP" BEL
        "my_kcpsm3/reg_loop_register_bit_4/DP" BEL
        "my_kcpsm3/reg_loop_register_bit_5/SP" BEL
        "my_kcpsm3/reg_loop_register_bit_5/DP" BEL
        "my_kcpsm3/reg_loop_register_bit_6/SP" BEL
        "my_kcpsm3/reg_loop_register_bit_6/DP" BEL
        "my_kcpsm3/reg_loop_register_bit_7/SP" BEL
        "my_kcpsm3/reg_loop_register_bit_7/DP" BEL
        "my_kcpsm3/memory_bit_0/G.S0" BEL "my_kcpsm3/memory_bit_0/F.S0" BEL
        "my_kcpsm3/memory_bit_0/F.S1" BEL "my_kcpsm3/memory_bit_0/G.S1" BEL
        "my_kcpsm3/memory_bit_1/G.S0" BEL "my_kcpsm3/memory_bit_1/F.S0" BEL
        "my_kcpsm3/memory_bit_1/F.S1" BEL "my_kcpsm3/memory_bit_1/G.S1" BEL
        "my_kcpsm3/memory_bit_2/G.S0" BEL "my_kcpsm3/memory_bit_2/F.S0" BEL
        "my_kcpsm3/memory_bit_2/F.S1" BEL "my_kcpsm3/memory_bit_2/G.S1" BEL
        "my_kcpsm3/memory_bit_3/G.S0" BEL "my_kcpsm3/memory_bit_3/F.S0" BEL
        "my_kcpsm3/memory_bit_3/F.S1" BEL "my_kcpsm3/memory_bit_3/G.S1" BEL
        "my_kcpsm3/memory_bit_4/G.S0" BEL "my_kcpsm3/memory_bit_4/F.S0" BEL
        "my_kcpsm3/memory_bit_4/F.S1" BEL "my_kcpsm3/memory_bit_4/G.S1" BEL
        "my_kcpsm3/memory_bit_5/G.S0" BEL "my_kcpsm3/memory_bit_5/F.S0" BEL
        "my_kcpsm3/memory_bit_5/F.S1" BEL "my_kcpsm3/memory_bit_5/G.S1" BEL
        "my_kcpsm3/memory_bit_6/G.S0" BEL "my_kcpsm3/memory_bit_6/F.S0" BEL
        "my_kcpsm3/memory_bit_6/F.S1" BEL "my_kcpsm3/memory_bit_6/G.S1" BEL
        "my_kcpsm3/memory_bit_7/G.S0" BEL "my_kcpsm3/memory_bit_7/F.S0" BEL
        "my_kcpsm3/memory_bit_7/F.S1" BEL "my_kcpsm3/memory_bit_7/G.S1" BEL
        "my_kcpsm3/stack_bit_0/G" BEL "my_kcpsm3/stack_bit_0/F" BEL
        "my_kcpsm3/stack_bit_1/G" BEL "my_kcpsm3/stack_bit_1/F" BEL
        "my_kcpsm3/stack_bit_2/G" BEL "my_kcpsm3/stack_bit_2/F" BEL
        "my_kcpsm3/stack_bit_3/G" BEL "my_kcpsm3/stack_bit_3/F" BEL
        "my_kcpsm3/stack_bit_4/G" BEL "my_kcpsm3/stack_bit_4/F" BEL
        "my_kcpsm3/stack_bit_5/G" BEL "my_kcpsm3/stack_bit_5/F" BEL
        "my_kcpsm3/stack_bit_6/G" BEL "my_kcpsm3/stack_bit_6/F" BEL
        "my_kcpsm3/stack_bit_7/G" BEL "my_kcpsm3/stack_bit_7/F" BEL
        "my_kcpsm3/stack_bit_8/G" BEL "my_kcpsm3/stack_bit_8/F" BEL
        "my_kcpsm3/stack_bit_9/G" BEL "my_kcpsm3/stack_bit_9/F";
PIN instance_name/DCM_INST_pins<20> = BEL "instance_name/DCM_INST" PINNAME
        CLKIN;
TIMEGRP clk = PIN "instance_name/DCM_INST_pins<20>";
TS_clk = PERIOD TIMEGRP "clk" 10 ns HIGH 50%;
TS_instance_name_CLKFX_BUF = PERIOD TIMEGRP "instance_name_CLKFX_BUF" TS_clk /
        0.5 HIGH 50%;
OFFSET = IN 6 ns BEFORE COMP "clk";
OFFSET = OUT 7.5 ns AFTER COMP "clk";
SCHEMATIC END;